SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 92

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

10.11.3
10.11.3.1
10.11.3.2
10.11.3.3
92
92
SAM3S8/SD8
SAM3S8/SD8
LDR and STR, register offset
Syntax
Operation
Restrictions
Load and Store with register offset.
where:
op
type
cond
Rt
Rn
Rm
LSL #n
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is
specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
In these instructions:
When Rt is PC in a word load instruction:
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
• if the instruction is conditional, it must be the last instruction in the IT block.
halfword-aligned address
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
LDR
STR
B
SB
H
SH
-
is one of:
Load Register.
Store Register.
is one of:
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is a register containing a value to be used as the offset.
is an optional shift, with n in the range 0 to 3.
“Address alignment” on page
“Conditional execution” on page
83.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
84.