SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 908

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SAM3SD8C

Manufacturer Part Number
SAM3SD8C
Description
Manufacturer
Atmel Corporation
Datasheets
35.7.1
Name:
Address:
Access:
This register can only be written if the bits WPSWS0 and WPHWS0 are cleared in
page
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB: CLKA, CLKB Source Clock Selection
908
908
DIVA, DIVB
0
1
2-255
PREA, PREB
0
0
0
0
0
0
0
0
1
1
1
Other
939.
31
23
15
7
SAM3S8/SD8
SAM3S8/SD8
PWM Clock Register
0
0
0
0
1
1
1
1
0
0
0
PWM_CLK
0x40020000
Read-write
0
0
1
1
0
0
1
1
0
0
1
30
22
14
6
0
1
0
1
0
1
0
1
0
1
0
29
21
13
5
CLKA, CLKB
CLKA, CLKB clock is turned off
CLKA, CLKB clock is clock selected by PREA, PREB
CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
Divider Input Clock
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
Reserved
28
20
12
4
DIVB
DIVA
27
19
11
3
“PWM Write Protect Status Register” on
26
18
10
2
PREB
PREA
25
17
9
1
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
24
16
8
0

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