AD9644 Analog Devices, AD9644 Datasheet - Page 2

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

AD9644
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 20
REVISION HISTORY
1/12—Rev. B to Rev. C
Change to General Description Section ........................................ 3
6/11—Rev. A to Rev. B
Added Figure 23 to Figure 40; Renumbered Sequentially ........ 16
Changes to Clock Input Considerations Section........................ 22
Added Figure 61 .............................................................................. 24
Changes to Digital Outputs and Timing Section ....................... 27
Added Figure 69 .............................................................................. 28
Changes to Output Test Modes Section ...................................... 29
Changes to SPI Accessible Features Section ............................... 32
ADC DC Specifications ............................................................... 4
ADC AC Specifications ............................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
ESD Caution ................................................................................ 10
ADC Architecture ...................................................................... 20
Analog Input Considerations .................................................... 20
Rev. C | Page 2 of 44
Built-In Self-Test (BIST) and Output Test .................................. 29
Serial Port Interface (SPI) .............................................................. 31
Memory Map .................................................................................. 33
Applications Information .............................................................. 42
Outline Dimensions ....................................................................... 43
4/11—Rev. 0 to Rev. A
Added Model -155 ......................................................... Throughout
Changes to Features Section and Figure 1 ..................................... 1
Changes to General Description Section ....................................... 3
Changes to Table 1 ............................................................................. 4
Changes to Table 2 ............................................................................. 5
Changes to Table 4 ............................................................................. 8
Additions to TPC Introductory Statement ................................. 13
Changes to Speed Grade ID Bits in Table 17 .............................. 31
Changes to Ordering Guide .......................................................... 40
6/10—Revision 0: Initial Version
Voltage Reference ....................................................................... 22
Clock Input Considerations ...................................................... 22
Channel/Chip Synchronization ................................................ 24
Power Dissipation and Standby Mode .................................... 24
Digital Outputs ........................................................................... 24
Built-In Self-Test (BIST) ............................................................ 29
Output Test Modes ..................................................................... 29
Configuration Using the SPI ..................................................... 31
Hardware Interface ..................................................................... 32
SPI Accessible Features .............................................................. 32
Reading the Memory Map Register Table ............................... 33
Memory Map Register Table ..................................................... 34
Memory Map Register Descriptions ........................................ 38
Design Guidelines ...................................................................... 42
Ordering Guide .......................................................................... 43
Data Sheet