AD9776A Analog Devices, AD9776A Datasheet - Page 28

• Manufacturer Part Number: AD9776A
• Description: Dual 12-Bit, 1 GSPS, Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9776A

• Resolution (bits): 12bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9776A/AD9778A/AD9779A
3-WIRE INTERFACE REGISTER MAP
Note that all unused register bits should be kept at the device default values.
Table 13.
Register
Name
Comm
Digital
Control
Sync
Control
PLL
Control
Misc.
Control
I DAC
Control
Aux
DAC1
Control
Q DAC
Control
Aux
DAC2
Control
Interrupt
Version
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
to
0x18
0x19
0x1F
Hex
Address
Decimal
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19 to 24
25
31
Bit 7
SDIO
bidirectional
Data format
DATACLK
delay mode
SYNC_I
enable
PLL enable
I DAC sleep
Auxiliary
DAC1 sign
Q DAC sleep
Auxiliary
DAC2 sign
Data timing
error IRQ
Interpolation Factor[1:0]
VCO Control Voltage[2:0] (read only)
Bit 6
LSB/MSB
first
Single port
Reserved
(set to 1)
SYNC_O
enable
PLL VCO Divide Ratio[1:0]
I DAC
power-
down
Auxiliary
DAC1
current
direction
Q DAC
power-
down
Auxiliary
DAC2
current
direction
Sync timing
error IRQ
DATACLK Delay[3:0]
SYNC_O Delay[3:0]
SYNC_I Delay[3:0]
PLL Band Select[5:0]
Bit 5
Software
reset
Real mode
SYNC_O
triggering
edge
Auxiliary
DAC1
power-
down
Auxiliary
DAC2
power-
down
Rev. B | Page 28 of 56
DATACLK Divide[1:0]
Q DAC Gain Adjustment[7:0]
I DAC Gain Adjustment[7:0]
Auxiliary DAC1 Data[7:0]
Auxiliary DAC2 Data[7:0]
Filter Modulation Mode[3:0]
Bit 4
DATACLK
Power-
down
mode
delay
enable
Data
timing
error type
Version[7:0]
PLL Loop Divide
Reserved
Ratio[1:0]
Bit 3
Auto
power-
down
enable
Inverse
sinc
enable
Data
timing
error
IRQ
enable
PLL Loop Bandwidth[4:0]
SYNC_O Divide[2:0]
SYNC_I Ratio[2:0]
Clock State[4:0]
SYNC_I Timing Margin[3:0]
Bit 2
DATACLK
invert
Sync
timing
error IRQ
enable
Data Timing Margin[3:0]
PLL Bias[2:0]
Bit 1
PLL lock
indicator
(read
only)
DATACLK
Delay[4]
TxEnable
invert
PLL VCO Drive[1:0]
Adjustment[9:8]
Adjustment[9:8]
Auxiliary DAC1
Auxiliary DAC2
Q DAC Gain
I DAC Gain
Data[9:8]
Data[9:8]
Bit 0
Zero
stuffing
enable
Q first
SYNC_O
Delay[4]
SYNC_I
Delay[4]
Internal
sync
loopback
Def.
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE7
0x52
0x1F
0xF9
0x01
0x00
0x00
0xF9
0x01
0x00
0x00
0x00
0x07