AD9776A Analog Devices, AD9776A Datasheet - Page 41

• Manufacturer Part Number: AD9776A
• Description: Dual 12-Bit, 1 GSPS, Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9776A

• Resolution (bits): 12bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

Configuring PLL Band Select with Temperature Sensing
The following procedure outlines a method for setting the PLL
band select value for a device operating at a particular temperature
that holds for a change in ambient temperature over the total
−40°C to +85°C operating range of the device without further
user intervention. Note that REFCLK must be applied to the
device during this procedure.
1.
2.
3.
4.
5.
This procedure requires temperature sensing upon start-up or
reset of the device to optimally choose the PLL band select
value that holds over the entire operating temperature range. If
the optimal band is in the range of 0 to 31 (lower VCO
frequency), refer to Table 24.
Table 24. Setting Optimal PLL Band, When Band Is in the
Lower Range (0 to 31)
If System Startup
Temperature Is
−40°C to −10°C
−10°C to +15°C
15°C to 55°C
55°C to 85°C
If the optimal band is in the range of 32 to 62 (higher VCO
frequency), refer to Table 25.
Table 25. Setting Optimal PLL Band, When Band Is in the
Higher Range (32 to 62)
If System Startup
Temperature Is
−40°C to −30°C
−30°C to −10°C
−10°C to +15°C
15°C to 55°C
55°C to 85°C
Program the values of N1 (Register 0x09, Bits[6:5]) and N2
(Register 0x09, Bits[4:3]), along with the PLL settings
shown in Table 22.
Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable
PLL auto mode.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x00, Bit 1) to go high. This should occur
within 5 ms.
Read back the 6-bit PLL band (Register 0x08, Bits[7:2]).
Based on the temperature when the PLL auto band select is
performed, set the PLL band indicated in either Table 24 or
Table 25 by rewriting the readback values into the PLL
Band Select parameter (Register 0x08, Bits[7:2]).
Set PLL Band as Follows
Set PLL band = readback band + 2
Set PLL band = readback band + 1
Set PLL band = readback band
Set PLL band = readback band − 1
Set PLL Band as Follows
Set PLL band = readback band
Set PLL band = readback band − 1
Set PLL band = readback band + 3
Set PLL band = readback band + 2
Set PLL band = readback band + 1
Rev. B | Page 41 of 56
Known Temperature Calibration with Memory
If temperature sensing is not available in the system, a factory
calibration at a known temperature is another method for
guaranteeing lock over temperature. Factory calibration can be
performed as follows:
1.
2.
3.
4.
5.
Set-and-Forget Device Option
If the PLL band select configuration methods described in
the previous sections cannot be implemented in a particular
system, there may be a screened device option that can satisfy
the system requirements. This allows the user to preload a
specific PLL band select value for all devices that holds over
temperature. Example REFCLK and VCO frequencies are
shown in Table 26.
Table 26. Typical VCO Frequency Range vs.
PLL Band Select Value
f
59.73335
61.44
67.2
76.8
80.01
81.92
92.16
112.0
119.4667
122.88
REFCLK
Program the values of N1 (Register 0x09, Bits[6:5]) and N2
(Register 0x09, Bits[4:3]), along with the PLL settings
shown in Table 22.
Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable
PLL auto mode.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x00, Bit 1) to go high. This should occur
within 5 ms.
Read back the 6-bit PLL band (Register 0x08, Bits[7:2]).
Based on the temperature when the PLL auto band select is
performed, store into nonvolatile memory the PLL band
indicated in either Table 24 or Table 25. On system power-
up or restart, load the stored PLL band value into the PLL
band select parameter (Register 0x08, Bits[7:2]).
(MHz)
f
955.7336
1966.08
1075.2
1228.8
1280
1310.72
1474.56
1792.0
955.7336
1966.08
VCO
AD9776A/AD9778A/AD9779A
(MHz)
Guaranteed
PLL Band
2
61
11
20
23
25
34
50
2
61
Total PLL
Divide Ratio
16
32
16
16
16
16
16
16
8
16