AD9776A Analog Devices, AD9776A Datasheet - Page 42

• Manufacturer Part Number: AD9776A
• Description: Dual 12-Bit, 1 GSPS, Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9776A

• Resolution (bits): 12bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9776A/AD9778A/AD9779A
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
The signal level can range from 400 mV p-p differential to
1.6 V p-p differential centered about a 400 mV input common-
mode voltage. Looking at the single-ended inputs, REFCLK+ or
REFCLK−, each input pin can safely swing from 200 mV p-p to
800 mV p-p about the 400 mV common-mode voltage. Although
these input levels are not directly LVDS compatible, REFCLK
can be driven by an offset ac-coupled LVDS signal, as shown in
Figure 73.
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 73. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, and then ac-coupled as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 74.
LVDS_P_IN
LVDS_N_IN
Figure 73. LVDS REFCLK Drive Circuit
0.1µF
0.1µF
50Ω
50Ω
V
CM
= 400mV
REFCLK–
REFCLK+
Rev. B | Page 42 of 56
A simple bias network for generating V
It is important to use CVDD18 and CGND for the clock bias
circuit. Any noise or other signal that is coupled onto the clock
is multiplied by the DAC digital input signal and can degrade
DAC performance.
TTL OR CMOS
CLK INPUT
287Ω
1kΩ
Figure 74. TTL or CMOS REFCLK Drive Circuit
Figure 75. REFCLK V
0.1µF
0.1µF
1nF
CM
Generator Circuit
V
CM
1nF
CM
50Ω
50Ω
= 400mV
is shown in Figure 75.
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
CM
CVDD18
CGND
= 400mV
REFCLK+
REFCLK–