AD9776A Analog Devices, AD9776A Datasheet - Page 30

• Manufacturer Part Number: AD9776A
• Description: Dual 12-Bit, 1 GSPS, Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9776A

• Resolution (bits): 12bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9776A/AD9778A/AD9779A
Register Name
Sync Control
Register
Address
0x03
0x03
0x03
0x03
0x04
0x04
0x04
0x05
0x05
0x05
0x06
0x06
0x07
0x07
0x07
0x07
Bits
7
6
5:4
3:0
7:4
3:1
0
7:4
3:1
0
7:4
3:0
7
6
5
4:0
Parameter
DATACLK delay mode
Reserved
DATACLK Divide[1:0]
Data Timing Margin[3:0]
DATACLK Delay[3:0]
SYNC_O Divide[2:0]
SYNC_O Delay[4]
SYNC_O Delay[3:0]
SYNC_I Ratio[2:0]
SYNC_I Delay[4]
SYNC_I Delay[3:0]
SYNC_I Timing Margin[3:0]
SYNC_I enable
SYNC_O enable
SYNC_O triggering edge
Clock State[4:0]
Rev. B | Page 30 of 56
Function
1: automatic data timing error detect mode.
Should always be set to 1.
DATACLK output divider value.
00: divide by 1.
01: divide by 2.
10: divide by 4.
11: divide by 1.
Sets the timing margin required to prevent the
data timing error IRQ bit from being asserted.
Sets delay of REFCLK input to DATACLK output (see
Table 29 for details).
The frequency of the SYNC_O signal is equal to
f
000: N = 32.
001: N = 16.
010: N = 8.
011: N = 4.
100: N = 2.
101: N = 1.
110: N = undefined.
111: N = undefined.
The SYNC_O Delay[4:0] value programs the value
of the delay line of the SYNC_O signal. The delay of
SYNC_O is relative to REFCLK. The delay line
resolution is 80 ps per step.
00000: nominal delay.
00001: adds 80 ps delay to SYNC_O.
00010: adds 160 ps delay to SYNC_O.
…
11111: Adds 2480 ps delay to SYNC_O.
This value controls the number of SYNC_I input
pulses required to generate a synchronization
pulse (see Table 30 for details).
The SYNC_I Delay[4:0] value programs the value of
the delay line of the SYNC_I signal. The delay line
resolution is 80 ps per step.
00000: nominal delay.
00001: adds 80 ps delay to SYNC_I.
00010: adds 160 ps delay to SYNC_I.
…
11111: adds 2480 ps delay to SYNC_I.
1: enables the SYNC_I input.
1: SYNC_O changes on REFCLK rising edge.
This value determines the state of the internal
clock generation state machine upon
synchronization.
0: manual data timing error detect mode.
1: enables the SYNC_O output.
0: SYNC_O changes on REFCLK falling edge.
DAC
/N, where N is set as follows:
Default
0
0
00
0000
0000
000
0
0000
000
0
0000
0000
0
0
0
0