ADP5043 Analog Devices, ADP5043 Datasheet - Page 18

• Manufacturer Part Number: ADP5043
• Description: Micro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
• Manufacturer: Analog Devices

ADP5043
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a dropping input voltage or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
LDO SECTION
The ADP5043 contains one LDO with a low quiescent current
that provides an output current up to 300 mA. The low, 15 μA
typical, quiescent current at no load makes the LDO ideal for
battery-operated portable equipment.
The LDO operates with an input voltage range of 1.7 V to
5.5 V. The wide operating range makes this LDO suitable for
a cascade configuration where the LDO supply voltage is
provided from the buck regulator.
The LDO also provides high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with a small 1 µF ceramic input and output capacitors.
The LDO is optimized to supply analog circuits by offering
better noise performance than the buck regulator.
Internally, an LDO consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is con-
trolled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
reducing the current flowing to the output.
SUPERVISORY SECTION
The ADP5043 provides microprocessor supply voltage super-
vision by controlling the reset input of the microprocessor.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
Rev. A | Page 18 of 32
problems with microprocessor code execution can be monitored
and corrected with a dual-watchdog timer.
Reset Output
The ADP5043 has an active-low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail that is no higher than 6 V. The
resistor should comply with the logic low and logic high voltage
level requirements of the microprocessor while supplying input
current and leakage paths on the nRSTO pin. A 10 kΩ pull-up
resistor is adequate in most situations.
The reset output is asserted when the monitored rail is below
the reset threshold (V
within the watchdog timeout period (t
asserted for the duration of the reset active timeout period (t
after the monitored rail rises above the reset threshold or after
the watchdog timer times out. Figure 44 illustrates the behavior
of the reset output, nRSTO, and it assumes that VOUT2 is
selected as the rail to be monitored and supplies the external pull-
up connected to the nRSTO output.
The reset threshold voltage and the sensed rail (VOUT1, VOUT2,
or AVIN) are factory programmed. Refer to Table 16 for a
complete list of the reset thresholds available for the ADP5043.
When monitoring the input supply voltage, AVIN, if the
selected reset threshold is below the UVLO level (factory
programmable to 2.25 V or 3.6 V) the reset output, nRSTO,
is asserted low as soon as the input voltage falls below the
UVLO threshold. Below the UVLO threshold, the reset output
is maintained low down to ~1 V VIN. This is to ensure that the
reset output is not released when there is sufficient voltage on the
rail supplying a processor to restart the processor operations.
Manual Reset Input
The ADP5043 features a manual reset input ( MR ) which, when
driven low, asserts the reset output. When MR transitions from
low-to-high, reset remains asserted for the duration of the reset
active timeout period before deasserting. The MR input has a
52 kΩ, internal pull-up, connected to AVIN, so that the input
is always high when unconnected. An external push-button
switch can be connected between MR and ground so that the
user can generate a reset. Debounce circuitry for this purpose is
integrated on chip. Noise immunity is provided on the MR input,
and fast, negative-going transients of up to 100 ns (typical) are
ignored. A 0.1 µF capacitor between MR and ground provides
additional noise immunity.
nRSTO
VOUT2
RSTO
1V
0V
0V
1V
0V
Figure 44. Reset Timing Diagram
V
TH
TH
t
t
), when WDI1 or WDI2 is not serviced
RP1
RP1
WD1
and t
WD2
Data Sheet
t
RD
). Reset remains
V
TH
t
RD
RP
)