ADP5043 Analog Devices, ADP5043 Datasheet - Page 20

• Manufacturer Part Number: ADP5043
• Description: Micro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
• Manufacturer: Analog Devices

ADP5043
Watchdog Status Indicator
In addition to the dual watchdog function, the ADP5043
features a watchdog status monitor available on the WSTAT pin.
This pin can be queried by the external processor to determine
the origin of a reset. WSTAT is an open-drain output.
WSTAT outputs a logic level depending on the condition
that has generated a reset. WSTAT is forced low if the reset
was generated because of a Watchdog 2 timeout. WSTAT is
pulled high, through external pull-up, for any other reset cause
(Watchdog 1 timeout, power failure or monitored voltage be
low threshold). The status monitor is automatically cleared
(set to logic level high) 10 seconds after the nRSTO low-to-high
transition (t
to read the WSTAT flag before t
Watchdog 2 reset.
The WSTAT flag is not updated in the event of a reset due to a
low voltage threshold detection or Watchdog 1 event occurring
within 10 seconds after an nRSTO low-to-high transition. In
this situation, WSTAT maintains the previous state (see the state
flow in Figure 47).
WDCLEAR
). The processor firmware must be designed
AVIN < VUVLO
TRANSITION
TRANSITION
TRANSITION
WDCLEAR
WDOG1 TIMEOUT
WSTAT TIMEOUT
STATE
STATE
STATE
(t
WD1
expiration after a
) AND
ALL ENx = HIGH
WSTAT = HIGH
WSTAT = HIGH
AVIN > VUVLO
END OF POR
WSTAT = 1
WSTAT = 1
POR
ALL REGULATORS AND SUPERVISORY
NO POWER APPLIED TO AVIN.
WDOG1 TIMEOUT
Figure 47. ADP5043 State Flow
(t
TIMEOUT
WDCLEAR
WSTAT
ALL ENx = LOW
(t
Rev. A | Page 20 of 32
WD1
TURNED OFF
NO POWER
AVIN < VUVLO
STANDBY
NORMAL
ACTIVE
)
)
RESET
VMON < VTH
INTERNAL CIRCUIT BIASED
REGULATORS AND
SUPERVISORY NOT ACTIVATED
TIMEOUT
WDOG2
The external processor can further distinguish a reset caused
by a Watchdog 1 timeout from a power failure, status monitor
WSTAT indicating a high level, by implementing a RAM check
or signature verification after reset. A RAM check or signature
failure indicates that a power failure has occurred, whereas a
RAM check or signature validation indicates that a Watchdog 1
timeout has occurred.
Table 10 shows the possible watchdog decoded statuses.
Table 10. Watchdog Status Decoding
WSTAT
High
High
Low
(t
WD2
SUPERVISOR ACTIVATED
END OF RESET
ALL REGULATORS AND
PULSE (t
)
RP1
WSTAT = LOW
END OF (t
TRANSITION
)
STATE
PULSE
RAM Checksum
Failed
Ok
Don't care
POFF
AVIN < VUVLO
)
WSTAT = 0
END OF RESET
RESET SHORT
AVIN < VUVLO
PULSE (t
POWER OFF
RP2
)
Reset Origin
Power failure
Watchdog 1
Watchdog 2
Data Sheet