ADP5043 Analog Devices, ADP5043 Datasheet - Page 26

• Manufacturer Part Number: ADP5043
• Description: Micro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
• Manufacturer: Analog Devices

ADP5043
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
where:
C
C
For the ADP5043, the total of (C
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near V
ground). The amount of transition loss is calculated by:
where t
switching node, SW. For the ADP5043, the rise and fall times of
SW are in the order of 5 ns.
If the equations and parameters previously given are used for
estimating the converter efficiency, it must be noted that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout, so a sufficient safety margin should be
included in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by:
where:
I
V
respectively.
I
Power dissipation due to the ground current is small and it
can be ignored.
LOAD
GND
GATE-P
GATE-N
IN
and V
is the ground current of the LDO regulator.
P
P
P
is the load current of the LDO regulator.
SW
TRAN
DLDO
is the PMOSFET gate capacitance.
is the NMOSFET gate capacitance.
RISE
= (C
OUT
= V
= [(V
and t
GATE-P
are input and output voltages of the LDO,
IN1
FALL
IN
× I
− V
+ C
are the rise time and the fall time of the
OUT1
OUT
GATE-N
× (t
) × I
) × V
RISE
LOAD
+ t
GATE-P
IN1
] + (V
FALL
2
× f
) × f
+ C
SW
IN
OUT1
× I
SW
GATE-N
GND
(and from V
) is ~150 pF.
)
OUT1
(10)
(11)
(12)
Rev. A | Page 26 of 32
to
Junction Temperature
The total power dissipation in the ADP5043 simplifies to:
In cases where the board temperature (T
thermal resistance parameter, θ
junction temperature rise. T
the formula:
The typical θ
38°C/W, see Table 7. A very important factor to consider is that
θ
standard, and real applications may use different sizes and
layers. It is important to maximize the copper used to remove
the heat from the device, and copper exposed to air dissipates heat
better than copper used in the inner layers. The thermal pad
(TP) should be connected to the ground plane with several vias
as shown in Figure 55.
If the case temperature can be measured, the junction
temperature is calculated by:
where:
T
θ
Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5043 power
dissipation (P
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
The reliable operation of the buck regulator and the LDO
regulator can be achieved only if the estimated die junction
temperature of the ADP5043 (Equation 14) is less than 125°C.
Reliability and mean time between failures (MTBF) is highly
affected by increasing the junction temperature. Additional
information about product reliability can be found in the
Analog Devices, Inc., Reliability
JA
JC
C
is the case temperature.
is based on a four-layer 4” × 3”, 2.5 oz copper, as per Jedec
is the junction-to-case thermal resistance provided in
P
T
T
D
J
J
= T
= T
= {[P
A
C
+ (P
+ (P
DBUCK
JA
D
) due to the losses of all channels by using
value for the 20-lead, 4 mm × 4 mm LFCSP is
D
D
× θ
+ P
× θ
JA
JC
DLDO1
)
)
J
, can be estimated using Equation 14.
+ P
J
is calculated from T
DLDO2
JA
Handbook.
, can be used to estimate the
]}
A
) is known, the
Data Sheet
A
and P
D
using
(13)
(14)
(15)