P87LPC768 NXP Semiconductors, P87LPC768 Datasheet - Page 26

• Manufacturer Part Number: P87LPC768
• Description: The P87LPC768 is a 20-pin single-chip microcontroller designed forlow pin count applications demanding high-integration, low costsolutions over a wide range of performance requirements
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
Table 3. CT1, CT0 Values
Interrupts
The P87LPC768 uses a four priority level interrupt structure. This
allows great flexibility in controlling the handling of the P87LPC768’s
many interrupt sources. The P87LPC768 supports up to 13 interrupt
sources.
Each interrupt source can be individually enabled or disabled by
setting or clearing a bit in registers IEN0 or IEN1. The IEN0
register also contains a global disable bit, EA, which disables all
interrupts at once.
Each interrupt source can be individually programmed to one of four
priority levels by setting or clearing bits in the IP0, IP0H, IP1, and
IP1H registers. An interrupt service routine in progress can be
Table 4. Summary of Interrupts
2002 Mar 12
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Serial Port Tx and Rx
Brownout Detect
I
KBI Interrupt
Comparator 2 interrupt
Watchdog Timer
A/D Converter
Comparator 1 interrupt
Timer 1 interrupt
2
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Any or all 1
Any or all 1
MASTRQ,
C Interrupt
SLAVEN,
MASTER
All 0
All 0
Description
CT1, CT0
1 0
0 1
0 0
1 1
TIRUN
0
1
0
1
The I
application wants to ignore the I
The I
The I
not, so that there is no checking for I
The I
Start and Stop conditions. This is the normal state for I
2
2
2
2
C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I
C interface is disabled.
C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do
C interface is enabled. Timer I runs during frames on the I
Flag Bit(s)
Interrupt
WDOVF
TI & RI
CMF2
CMF1
ADCI
BOF
ATN
KBF
TF0
TF1
IE0
IE1
–
(Machine Cycles)
Min Time Count
7
6
5
4
Address
Vector
000Bh
001Bh
002Bh
003Bh
005Bh
0003h
0013h
0023h
0033h
0043h
0053h
0063h
0073h
2
C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.
2
C being “hung.” This configuration can be used for very slow I
24
EWD (IEN0.6)
EBO (IEN0.5)
Enable Bit(s)
EKB (IEN1.1)
EAD (IEN1.4)
EX0 (IEN0.0)
ET0 (IEN0.1)
EX1 (IEN0.2)
ET1 (IEN0.3)
EC2 (IEN1.2)
EC1 (IEN1.5)
ETI (IEN 1.7)
EI2 (IEN1.0)
ES (IEN0.4)
OPERATING MODE
Interrupt
interrupted by a higher priority interrupt, but not by another interrupt
of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two
requests of different priority levels are received simultaneously, the
request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an
internal polling sequence determines which request is serviced. This
is called the arbitration ranking. Note that the arbitration ranking is
only used to resolve simultaneous requests of the same priority level.
Table 3 summarizes the interrupt sources, flag bits, vector
addresses, enable bits, priority bits, arbitration ranking, and whether
each interrupt may wake up the CPU from Power Down mode.
(for 100 kHz I
CPU Clock Max
2
C operation.
8.4 MHz
7.2 MHz
6.0 MHz
4.8 MHz
IP0H.0, IP0.0
IP0H.1, IP0.1
IP0H.2, IP0.2
IP0H.3, IP0.3
IP0H.4, IP0.4
IP0H.5, IP0.5
IP1H.0, IP1.0
IP1H.1, IP1.1
IP1H.2, IP1.2
IP0H.6, IP0.6
IP1H.4, IP1.4
IP1H.5, IP1.5
Ip1H.7, IP1.7
2
Interrupt
C, and is cleared by transitions on SCL, and by
Priority
2
C)
Arbitration
13 (lowest)
1 (highest)
Ranking
10
12
11
4
7
2
5
8
3
6
9
(Machine Cycles)
Timeout Period
P87LPC768
1023
1022
1021
1020
Preliminary data
2
Power Down
C operation.
Wakeup
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
2
C