BSH103 NXP Semiconductors, BSH103 Datasheet - Page 3

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

BSH103

Manufacturer Part Number
BSH103
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. T
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Device mounted on printed-circuit board with an R
4. Device mounted on printed-circuit board with an R
1998 Feb 11
handbook, halfpage
V
V
I
I
P
T
T
Source-drain diode
I
I
SYMBOL
D
DM
S
SM
stg
j
DS
GS
tot
N-channel enhancement mode
MOS transistor
P tot
(W)
s
0.6
0.4
0.2
is the temperature at the soldering point of the drain lead.
0
0
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
operating junction temperature
source current (DC)
peak pulsed source current
Fig.2 Power derating curve.
40
80
PARAMETER
120
T s ( C)
MGM190
160
th a-tp
th a-tp
3
(ambient to tie-point) of 27.5 K/W.
(ambient to tie-point) of 90 K/W.
T
T
T
note 2
T
T
note 2
s
s
amb
amb
s
handbook, halfpage
= 80 C; note 1
= 80 C
= 80 C
(1) R
(2) Pulsed.
= 0.01; T
= 25 C; note 3
= 25 C; note 4
CONDITIONS
10
10
10
I DS
(A)
10
DSon
10
1
1
2
3
1
s
limitation.
= 80 C.
P
(1)
t p
T
Fig.3 SOAR.
1
=
t p
T
t
55
55
MIN.
DC
10
Product specification
30
0.85
3.4
0.5
0.75
0.54
+150
+150
0.5
2
V DS (V)
8
MAX.
BSH103
(2)
MBK502
10
V
V
A
A
W
W
W
A
A
2
C
C
UNIT

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