STM32F100RB STMicroelectronics, STM32F100RB Datasheet - Page 14

• Manufacturer Part Number: STM32F100RB
• Description: Mainstream Value line, ARM Cortex-M3 MCU with 128 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F100RB

• Peripherals Supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• Conversion Range: 0 to 3.6 V
• 16-bit, 6-channel Advanced-control Timer: up to 6 channels for PWM output, dead time generation and emergency stop
• Systick Timer: 24-bit downcounter

Description
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Overview
ARM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F100xx value line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Embedded Flash memory
Up to 128 Kbytes of embedded Flash memory is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Embedded SRAM
Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F100xx value line embeds a nested vectored interrupt controller able to handle
up to 41 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
and 16 priority levels.
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This hardware block provides flexible interrupt management features with minimal interrupt
latency.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
®
Cortex™-M3 core with embedded Flash and SRAM
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Doc ID 16455 Rev 6