STM8L152C8 STMicroelectronics, STM8L152C8 Datasheet - Page 100

• Manufacturer Part Number: STM8L152C8
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L152C8

• Operating Power Supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
• Temp. Range: −40 to 85, 105 or 125 °C
• 5 Low Power Modes: Wait, Low power run (5.9 μA), Low power wait (3 μA), Active-halt with full RTC (1.4 μA), Halt (400 nA)
• Dynamic Power Consumption: 200 μA/MHz+330 μA
• Ultra Low Leakage Per I/0: 50 nA
• Max Freq: 16 MHz, 16 CISC MIPS peak
• Lcd: 8x40 or 4x44 w/ step-up converter

Electrical parameters
9.3.8
Table 43.
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.
4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.
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t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
t
t
h(NSS)
t
su(MI)
t
v(SO)
v(MO)
h(MO)
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(2)(3)
(2)
(2)(4)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
conditions summarized in
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
SPI1 characteristics
SPI1 clock frequency
SPI1 clock rise and fall
time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
Section
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Master mode,
f
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
MASTER
Doc ID 17943 Rev 4
9.3.1. Refer to I/O port characteristics for more details on
= 8 MHz, f
Conditions
SYSCLK
SCK
(1)
= 4 MHz
frequency and V
Table 43
4 x 1/f
are derived from tests
Min.
105
STM8L15xx8, STM8L15xR6
80
30
15
30
15
0
3
0
1
SYSCLK
0
-
-
-
-
DD
supply voltage
3x 1/f
Max.
145
30
60
20
SYSCLK
8
8
-
-
-
-
-
-
-
-
-
Unit
MHz
ns