STM8L152C8 STMicroelectronics, STM8L152C8 Datasheet - Page 15

• Manufacturer Part Number: STM8L152C8
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L152C8

• Operating Power Supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
• Temp. Range: −40 to 85, 105 or 125 °C
• 5 Low Power Modes: Wait, Low power run (5.9 μA), Low power wait (3 μA), Active-halt with full RTC (1.4 μA), Halt (400 nA)
• Dynamic Power Consumption: 200 μA/MHz+330 μA
• Ultra Low Leakage Per I/0: 50 nA
• Max Freq: 16 MHz, 16 CISC MIPS peak
• Lcd: 8x40 or 4x44 w/ step-up converter

STM8L15xx8, STM8L15xR6
3.2
3.2.1
3.2.2
Central processing unit STM8
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
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Addressing
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Instruction set
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Interrupt controller
The high density and medium+ density STM8L15xxdevices feature a nested vectored
interrupt controller:
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Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16 Mbyte linear memory space
16-bit stack pointer - access to a 64 Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
Doc ID 17943 Rev 4
Functional overview
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