STM8L152C8 STMicroelectronics, STM8L152C8 Datasheet - Page 16

• Manufacturer Part Number: STM8L152C8
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L152C8

• Operating Power Supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
• Temp. Range: −40 to 85, 105 or 125 °C
• 5 Low Power Modes: Wait, Low power run (5.9 μA), Low power wait (3 μA), Active-halt with full RTC (1.4 μA), Halt (400 nA)
• Dynamic Power Consumption: 200 μA/MHz+330 μA
• Ultra Low Leakage Per I/0: 50 nA
• Max Freq: 16 MHz, 16 CISC MIPS peak
• Lcd: 8x40 or 4x44 w/ step-up converter

Functional overview
3.3
3.3.1
3.3.2
Note:
16/126
Reset and supply management
Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (V
supply pins must be connected as follows:
●
●
●
●
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR). For the device sales types without the “D” option (see
information
device operates between 1.8 and 3.6 V, BOR is always active and ensures proper operation
starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading
process starts, either to confirm or modify default thresholds, or to disable BOR permanently
(in which case, the V
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains in
reset state when V
any external reset circuit.
For device sales types with the “D” option (see
BOR is permanently disabled and the device operates between 1.65 and 3.6 V. In this case
it is not possible to enable BOR through the option bytes.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
DD
DD
/V
/V
V
for I/Os and for the internal regulator. Provided externally through V
corresponding ground pin is V
must not be left unconnected.
V
voltage to be applied to V
connected to V
V
externally through V
V
externally through V
SS1
SSA
REF+
REF+
DDA
DDA
, V
, V
power supply and compares it to the V
is higher than the V
, V
(for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
scheme), it is coupled with a brownout reset (BOR) circuitry. It that case the
DD1
DDA
REF-
, V
= 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
DD
(for ADC1): external reference voltage for ADC1. Must be provided
SS2
DD
DD
is below a specified threshold, V
, V
and V
min. value at power-down is 1.65 V).
DD2
REF+
REF+
, V
SS
.
PVD
DDA
and V
Doc ID 17943 Rev 4
SS3
, respectively.
threshold. The interrupt service routine can then generate
is 1.8 V when the ADC1 is used). V
, V
DD
SS
REF-
. V
DD3
/V
DDA
SS1
, V
pin.
/V
SS4
drops below the V
SS2
Section 11: Ordering information
, V
/V
PVD
DD4
SS3
= 1.65 to 3.6 V: external power supply
POR/PDR
threshold. This PVD offers 7 different
/V
SS4
and V
Section 11: Ordering
PVD
or V
STM8L15xx8, STM8L15xR6
DD
BOR
threshold and/or when
DD1
). The external power
DDA
, without the need for
/V
DD
DD2
and V
pins, the
/V
DD3
SSA
scheme)
/V
must be
DD4