ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 103

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
One-pulse mode
One-pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one-pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure:
To use one-pulse mode:
1.
2.
3.
Figure 52. One-pulse mode cycle
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1.
2.
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the opposite column).
Select the following in the CR1 register:
–
–
–
Select the following in the CR2 register:
–
–
–
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
Set the OPM bit.
Select the timer clock CC[1:0] (see
event occurs
on ICAP1
Doc ID 12321 Rev 5
Counter
= OC1R
When
When
One-pulse mode cycle
Table 50: Clock control bits on page
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
ICR1 = Counter
ICF1 bit is set
to FFFCh
On-chip peripherals
110).
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