ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 173

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
Address matched: the interface generates in sequence the following:
●
●
●
The Status Register has to be read to clear the event flag associated with the interrupt
An interrupt will be generated only if the interrupt enable bit is set in the Control Register
Slaves 1 and 2 have a common interrupt and the Slave 3 has a separate interrupt.
At the end of write operation, I2C3S is temporarily disabled by hardware by setting BusyW
bit in CR2. The byte count register, status register and current address register should be
saved before resetting BusyW bit.
Slave reception (write operations)
Byte Write: The Slave address is followed by an 8-bit byte address. Upon receipt of this
address an acknowledge is generated, address is moved into the current address register
and the 8 bit data is clocked in. Once the data is shifted in, a DMA request is generated and
the data is written in the RAM. The addressing device will terminate the write sequence with
a stop condition. Refer to
Page Write: A page write is initiated in similar way to a byte write, but the addressing device
does not send a stop condition after the first data byte. The page length is programmed
using bits 7:6 (PL[1:0]) in the Control Register1.
The current address register value is incremented by one every time a byte is written. When
this address reaches the page boundary, the next byte will be written at the beginning of the
same page. Refer to
Slave transmission (Read operations)
Current address read: The current address register maintains the last address accessed
during the last read or write operation incremented by one.
During this operation the I2C slave reads the data pointed by the current address register.
Refer to
Random read: Random read requires a dummy byte write sequence to load in the byte
address. The addressing device then generates restart condition and resends the device
address similar to current address read with the read/write bit high. Refer to
Some types of I2C masters perform a dummy write with a stop condition and then a current
address read.
In either case, the slave generates a DMA request, sends an acknowledge and serially
clocks out the data.
When the memory address limit is reached the current address will roll over and the random
read will continue till the addressing master sends a stop condition.
Sequential read: Sequential reads are initiated by either a current address read or a
random address read. After the addressing master receives the data byte it responds with
an acknowledge. As long as the slave receives an acknowledge it will continue to increment
the current address register and clock out sequential data bytes.
An Acknowledge pulse
Depending on the LSB of the slave address sent by the master, slaves enter transmitter
or receiver mode.
Send an interrupt to the CPU after completion of the read/write operation after
detecting the Stop/ Restart condition on the SDA line.
Figure
78.
Figure
Figure 76
77.
Doc ID 12321 Rev 5
On-chip peripherals
Figure
79.
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