ST7232AJ2 STMicroelectronics, ST7232AJ2 Datasheet - Page 105

• Manufacturer Part Number: ST7232AJ2
• Description: 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST7232AJ2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
EOC SPEED ADON
7
ADC
ADC
= f
= f
CPU
CPU
/4
/2
0
CH3
CH2
CH1
CH0
0
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
D9
7
7
0
Channel Pin*
D8
0
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
D7
0
D6
0
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D5
0
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D4
0
CH1
ST7232A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D3
D1
105/157
CH0
D2
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1