TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 737

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

24.3.1.3
24.3.1.4
bly terminated during auto programming/erasing or abnormal termination in the automatic operation.
fore, when the RESET input pin of this device is set to VIL or when the CPU is reset due to any over-
flow of the watch dog timer, the flash memory will return to the read mode terminating any automatic op-
eration that may be in progress. It should also be noted that applying a hardware reset during an automat-
ic operation can result in incorrect rewriting of data. In such a case, be sure to perform the rewriting again.
will read the reset vector data from the flash memory and starts operation after the reset is removed.
(1)
A hardware reset is used to cancel the operational mode set by the command write operation when forci-
The flash memory has a reset input as the memory block and it is connected to the CPU reset signal. There-
Refer to Section "1.2.1 Reset Operation" for CPU reset operations. After a given reset input, the CPU
Reset (Hardware reset)
Commands
not be changed to a "1" data cell. For changing "0" data cells to "1" data cells, it is necessary to per-
form an erase operation.
TMPM363F10FG contains 128 words in a page. A 128 word block is defined by the same [31:9] ad-
dress. It starts from the address [8:0] = 0x00 and ends at the address [8:0] = 0x1FF. This program-
ming unit is hereafter referred to as a "page".
by the CPU is required. The state of automatic page programming (whether it is in writing opera-
tion or not) can be checked by FCFLCS [0] <RDY/BSY>.
mode. If it is desired to interrupt the automatic page programming, use the hardware reset function.
If the operation is stopped by a hardware reset operation, it is necessary to once erase the page and
then perform the automatic page programming again because writing to the page has not been normal-
ly terminated.
gramming can be performed twice or more. Note that rewriting to a page that has been once written
requires execution of the automatic block erase or automatic chip erase command before executing
the automatic page programming command again. Note that an attempt to rewrite a page two or
more times without erasing the content may cause damages to the device.
grammed to confirm that it has been correctly written.
cycle is completed. After the fifth bus write cycle, data will be written sequentially starting from
the next address of the address specified in the fourth bus write cycle (in the fourth bus write cycle,
the page top address will be command written) (32 bits of data is input at one time). Be sure to use
Note 3: For the command sequencer to recognize a command, the device must be in the read
Note 4: Upon issuing a command, if any address or data is incorrectly written, be sure to per-
Writing to a flash memory device is to change "1" data cells to "0" data cells. Any "0" data cell can-
The automatic page programming function of this device writes data of each page. The
Writing to data cells is automatically performed by an internal sequencer and no external control
Also, any new command sequence is not accepted while it is in the automatic page programming
The automatic page programming operation is allowed only once for a page already erased. No pro-
No automatic verify operation is performed internally to the device. So, be sure to read the data pro-
The automatic page programming operation starts when the third bus write cycle of the command
Automatic Page Program
the command. While it may cause an abnormal termination of the command sequence,
it also may cause an incorrect recognition of the command.
mode prior to executing the command. Be sure to check before the first bus write cycle
where FCFLCS <RDY / BSY> is set to "1". It is recommended to subsequently execute a
Read command.
form a software reset to return to the read mode again.
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TMPM363F10FG