TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 410

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.6
Data Format
12.6.2
12.6.3
12.6.2.1
12.6.2.2
ting the SCxMOD2<SBLEN>. The length of the STOP bit data is determined as one-bit when it is received re-
gardless of the setting of this bit.
The parity bit can be added only in the 7- or 8-bit UART mode.
Setting "1" to SCxCR<PE> enables the parity.
The SCxCR<EVEN> selects either even or odd parity.
The length of the STOP bit in the UART transmission mode can be selected from one bit or two bits by set-
transmit buffer.
mode SCxMOD<TB8> in the 8-bit UART mode.
while in the 8-bit UART mode, it is compared with the one in SCxCR<RB8>.
Parity Control
STOP Bit Length
Upon data transmission, the parity control circuit automatically generates the parity with the data in the
After data transmission is complete, the parity bit will be stored in SCxBUF<TB7> in the 7-bit UART
The <PE> and <EVEN> settings must be completed before data is written to the transmit buffer.
If the received data is moved from the receive shift register to the receive buffer, a parity is generated.
In the 7-bit UART mode, the generated parity is compared with the parity stored in SCxBUF<RB7>,
If there is any difference, a parity error occurs and the <PERR> of the SCxCR register is set to "1".
In use of the FIFO, <RERR> indicates that a parity error was generated in one of the received data.
Transmission
Receiving Data
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TMPM364F10FG