TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 638

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.6
Register
18.6.4
31
30
29-7
6
5
4
3
2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Host Controller sets the corresponding bit in this register. When the bit is set, a hardware interrupt is gener-
ated if the interrupt is enabled in the HcInterruptEnable register and the MasterInterruptEnable bit is set. The
Host Controller Driver may clear specific bits in this register by writing "1" to bit positions to be cleared.
The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit.
−
OC
−
RHSC
FNO
UE
RD
SF
WDH
SO
This register provides status on various events that cause hardware interrupts. When an event occurs, the
Bit Symbol
HcInterruptStatus Register
31
23
15
7
-
-
-
-
−
R/W
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(HCD)
Type
RHSC
OC
30
22
14
0
6
0
-
-
−
R/W
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
(HC)
Reserved
Filed name:Ownership Change
This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
This event, when unmasked, will always generate an System Management Interrupt (SMI) immedi-
ately.
This bit is tied to 0 when the SMI pin is not implemented.
Reserved
Filed name:Root Hub Status Change
This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[Numberof-
DownstreamPort] has changed.
Filed name:Frame Number Overflow
This bit is set when the MSB of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0,
and after HccaFrameNumber has been updated.
Filed name:Unrecoverable Error
This bit is set when HC detects a system error not related to USB. HC should not proceed with
any processing nor signaling before the system error has been corrected. HCD clears this bit af-
ter HC has been reset.
Filed name:Resume Detected
This bit is set when HC detects that a device on the USB is asserting resume signaling. It is the tran-
sition from no resume signaling to resume signaling causing this bit to be set. This bit is not set
when HCD sets the USBRESUME state.
Filed name:Startof Frame
This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. HC al-
so generates a SOF token at the same time
Filed name:Writeback Done Head
This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. Further updates
of the HccaDoneHead will not occur until this bit has been cleared. HCD should only clear this bit
after it has saved the content of HccaDoneHead.
Filed name:Scheduling Overrun
This bit is set when the USB schedule for the current Frame overruns and after the update of Hcca-
FrameNumber. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommand-
Status to be incremented.
FNO
29
21
13
5
0
-
-
-
Page 612
UE
28
20
12
4
0
-
-
-
RD
27
19
11
3
0
-
-
-
Function
SF
26
18
10
2
0
-
-
-
WDH
25
17
9
1
0
-
-
-
TMPM364F10FG
SO
24
16
8
0
0
-
-
-