TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 600

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.8
Bit Configuration
16.8
must have the same baud rate and bit length. At different clock frequencies of the individual controllers, the baud
rate has to be adjusted by the above-mentioned parameters. In the bit timing logic, the conversion of the parame-
ters to the required bit timing is implemented. The configuration registers CANBCR1 and CANBCR2 contain the
data about bit timing. Its definition corresponds to the CAN specification 2 (equivalent to Intel 82527).
plied as the clock for CAN baud rate generation. If f
the sampled bit level. The information processing time is equal to three CAN system clock cycles.
The length of a bit is determined by the parameters TSEG1, TSEG2, and BRP. All controllers on the CAN bus
Figure 16-12 shows CAN bit timing.
T
1 × T
f
The synchronization segment SYNCSEG always has the length of one T
The baud rate is defined by :
Information processing time (IPT) is the time segment starting with the sample point reserved for processing of
Note:<TSEG1[3:0]> and <TSEG2[2:0]> are values of the CANBCR2 register. It is not T
OSC
SCL
Bit Configuration
BR=
SYNCSEG
is the clock for CAN baud rate generation. The clock obtained by dividing the system clock f
SCL
(CAN system clock) is defined by :
= 1 × T
SJW
((<TSEG1[13:0]>+1)+(<TSEG2[2:0]>+1)+1)×T
Q
(T
Q
: time quantum)
T
SCL
Figure 16-12 CAN Bit Timing
=
TSEG1
1 bit time
<BRP[9:0]>+1
Page 574
SYS
f
1
osc
= 48MHz then f
Sample point
OSC
Q
.
= 12MHz.
IPT
Q
unit value.
TSEG2
TMPM364F10FG
SCL
SJW
SYS
by 4 is sup-