TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 190

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

9 16-bit Timer/Event Counters (TMRBs)
9.5.3
9.5.4
Timer registers (TB0RG0, TB0RG1)
Capture Control
two registers are built into each channel. If the comparator detects a match between a value set
in this timer register and that in a UC0 up-counter, it outputs the match detection signal.
TB0CP1 capture registers. The timing to latch data is specified by TB0MOD <TB0CPM1:0>.
register; specifically, UC0 values are taken into the TB0CP0 capture register each time “0” is
written to TB0MOD<TBCP0>. To use this capability, the prescaler must be running
(TB0RUN<TBPRUN> = “1”).
TB0RG0 and TB0RG1 are registers for setting values to compare with up-counter values and
This is a circuit that controls the timing to latch UC0 up-counter values into the TB0CP0 and
Software can also be used to capture values from the UC0 up-counter into the capture
•
double-buffered configuration. The two registers use TB0CR<TBWBF> to control the
enabling/disabling of double buffering. If <TBWBF> = “0”, double buffering is disabled and if
<TBWBF> = “1”, it is enabled. If double buffering is enabled, data is transferred from
register buffer to the TB0RG0 and TB0RG1 timer registers when there is a match between
UC0 and TB0RG1.
•
the double buffer.
•
data transfer instruction written twice in the order of low-order 8 bits followed by high-order
8 bits can be used.
address. If <TBWBF> = “0,” the same value is written to TB0RG0, TB0RG1 and each
register buffer; if <TBWBF> = “1,” the value is only written to each register buffer. Therefore,
in order to write an initial value to the timer register, the register buffers must be set to
“disable”. Then set <TBWBF> = “1”and write the following data to the register.
•
TB0RG0 and TB0RG1 of this timer registers are paired with register buffer - the
The values of TB0RG0 and TB0RG1 become undefined after a reset. A reset disables
1) When not using double-buffering
To write data to the timer registers, either a 2-byte data transfer instruction or a 1-byte
2) When using double-buffering
TB0RG0/ TB0RG1 and the register buffer0/ register buffer1 are assigned to the same
Note: The value of TB0RG0/1 must be set as TB0RG0 < TB0RG1 in PPG mode.
Configuration
Default setting
Register setting
Interrupt
INTTB00 is generated by UP0 count value matching with TB0RG0 value.
INTTB01 is generated by UP0 count value matching with TB0RG1 value.
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