TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 238

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10 16-bit Multi-purpose Timers (MPTs)
10.5.3
10.5.4
MTUC0 is a 16-bit binary counter.
two registers are built into each channel. If the comparator detects a match between a value set
in this timer register and that in a MTUC0 up-counter, it outputs the match detection signal.
Up-counter (MTUC0)
Timer registers (MT0RG0, MT0RG1)
MT0RG0 and MT0RG1 are registers for setting values to compare with up-counter values and
Source clock
either three types φT1, φT4 and φT16 of prescaler output clock or the external clock of the
MTTB0IN pin.
Count start/ stop
<MTRUN> = “1”, and stops counting and clears counter value if <MTRUN> = “0”.
Timing to clear MTUC0
MTUC0 overflow
Configuration
double-buffered configuration. The two registers use MT0TBCR<MTTBWBF> to control the
enabling/disabling of double buffering. If <MTTBWBF> = “0”, double buffering is disabled
and if <MTTBWBF> = “1”, it is enabled. If double buffering is enabled, data is transferred
from register buffer to the MT0RG0 and MT0RG1 timer registers when there is a match
between MTUC0 and MT0RG1.
Default setting
the double buffer.
MTUC0 source clock, specified by MT0TBMOD<MTTBCLK1:0>, can be selected from
Counter operation is specified by MT0RUN<MTRUN>. MTUC0 starts counting if
1) When a compare match is detected
2) When MTUC0 stops
MTUC0 stops counting and clears counter value if MT0RUN <MTRUN> = “0”.
If MTUC0 overflow occurs, the INTMTTB00 overflow interrupt is generated.
MT0RG0 and MT0RG1 of this timer registers are paired with register buffer - the
The values of MT0RG0 and MT0RG1 become undefined after a reset. A reset disables
By setting MT0TBMOD<MTTBCLE> = “1”, MTUC0 is cleared in case the comparator
detects a match between counter value and the value set in MT0RG1. MTUC0 operates
as a free-running counter if MT0TBMOD<MTTBCLE> = “0”.
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