TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 245

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10.6.3 Up-counter (MTUC0)
MTUC0 is a 16-bit binary counter.
Figure 10-4 Count-up/ count clearing when source clock φT0 is selected.
Source clock
four types φT0, φT 1, φT2 and φT4 of prescaler output clock.
Count start/ stop
<MTRUN> = “1”, and stops counting and clears counter value if <MTRUN> = “0”.
from 0.
Timing to clear the count
“0”.
stops and is cleared.
Count up and count clear operation
clock φT0 is selected and when source clock φT1, φT2 or φT4 is selected.
and the clear count. Thus a value of the period setup is set to M＋1.
1) When source clockφT0 is selected
MTUC0 source clock, specified by MT0IGCR<IGCLK1:0>, can be selected from either
Counter operation is specified by MT0RUN<MTRUN>. MTUC0 starts counting if
Also, counter is cleared if MT0IGRESTA<IGRESTA> = “1”, and then restarts count-up
1) When a comparing is matched.
2) When counter stops
By setting MT0RUN<MTRUN>=”0”, counter stops and is cleared.
3) When counter restart
By setting MT0IGRESTA<IGRESTA>=”1”, counter is cleared and starts counting up from
4) When trigger start mode is set.
In the trigger start mode, by setting MT0IN pin is driven to the specified stop level, counter
Here is the description of count and clear operation and period setup both when source
When source clock φT0 is selected, two source clocks are required for the match count
When the comparator detects a match between up-counter value and a value set in
MT0IGRG4, counter is cleared.
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TMPM380/M382