ADRF6702 Analog Devices, Inc., ADRF6702 Datasheet - Page 13

• Manufacturer Part Number: ADRF6702
• Description: 1550 Mhz To 2150 Mhz Quadrature Modulator With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
REGISTER 4—CHARGE PUMP, PFD AND
REFERENCE PATH CONTROL
With R4[2:0] set to 100, the on-chip Charge Pump, PFD and
Reference Path Control register is programmed as shown in
figure 43.
The charge pump current is controlled by the base charge pump
current (I
multiplier (I
The base charge pump current can be set using an internal or
external resistor (according to DB18 of Register 4). When using
an external resistor, the value of I
to the following table.
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, 4) of the charge pump base current. The
multiplying value (I
DB11 and DB10 in register 4.
The PFD phase offset multiplier (θ
DB16-DB12 of Register 4, will cause the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by the following equation:
R
ΔΦ [deg] = 22 .5
SET
CP,BASE
[ ]
Ω =
CP,MULT
), and the value of the charge pump current
⎡
⎢
⎣
217 .4 × I
).
CP,MULT
I
θ
250
CP , MULT
PFD ,OFS
) is equal to 1 plus the value of bits
CP ,BASE
CP,BASE
⎤
⎥
⎦
PFD,OFS
−
37 .8
can be varied according
), which is set by bits
Rev. PrE | Page 13 of 18
Finally, the phase offset can be either positive or negative
depending on the value of DB17 in register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2X,
1X, 0.5X, or 0.25X. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The ADRF6702 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals.
The default mode is to provide a lock-detect output to allow the
user to verify when the PLL has locked to the target frequency.
In addition, several other internal signals may be passed to the
MUXOUT pin as described in figure 43.
ADRF6702