ADRF6702 Analog Devices, Inc., ADRF6702 Datasheet - Page 7

• Manufacturer Part Number: ADRF6702
• Description: 1550 Mhz To 2150 Mhz Quadrature Modulator With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

Pin Nr.
1,10,17,22,
27,29,34
2,9, 40
3
4, 7,11,15,20,
21,23,24,25,2
8,30,31,35
5
6
8
12
13
14
16
18,19, 32,33
26
36
37,38
39
Preliminary Technical Data
Mnemonic
VDD
DECL
CP
GND
R
REFIN
MUXOUT
DATA
CLK
LE
ENOP
QP, QN, IN,
IP
RFOUT
LOSEL
LON, LOP
VTUNE
EP
SET
Description
Power Supply: Power supply voltage range is 4.75 V to 5.25 V. Each pin should be decoupled with a 100 pf and
0.1uF capacitors located close to the pin.
Internal Decoupling Nodes: Connect a 100 pF and a 0.1uF capacitor between each of these pins and ground.
Charge Pump: Chargepump Output Pin. Connect to V
Ground: Connect these pins to a low impedance ground planeGND
Charge Pump Current: The nominal charge pump current can be set to either 250 uA, 500 uA, 750 uA or 1 mA
using DB10 and DB11 of Register 4 and by setting DB18 to 0 (Internal Reference Current). In this mode, no external
R
according to the equation.
Where I
- Charge Pump, PFD and Reference Path Control.
Refence Input: Nominal input level is 1Vpp. Input range is 10 MHz to 160 MHz.
Multiplexer Output: This output can be programmed to provide the Reference Output signal or the Lock Detect
signal. The output is selected by programming the appropriate register.
Serial Data Input: The serial data input is loaded MSB first with the three LSBs being the control bits.
Serial Clock Input: This serial clock input is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable: When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six
registers, the relevant latch being selected by the first three control bits of the 24-bit word.
Modulator Output Enable/Disable
Modulator Baseband Inputs: Differential In-Phase and Quadrature Baseband Inputs. These high impedance
inputs should be dc-biased to 0.5 V.
RF Output: Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to its load.
LO Select: This digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and
LON become inputs if the LOSEL pin is set low AND the LDRV bit of Register 5 is set low. External LO drive must be a
2XLO. In addition to setting LOSEL and LDRV low and providing an external 2XLO, the LXL bit of Register 5 (DB4)
must be set to 1 to direct the external LO to the IQ Modulator. LON and LOP become outputs when LOSEL is high
OR if the LDRV bit of Register 5 (DB3) is set high. A 1X or 2X LO output can be selected by setting the LDIV bit of
Register 5 (DB5) to 1 or 0 respectively.
X = Don’t Care
LOSEL should not be left floating.
Local Oscillator Input/Output: The internally generated 1XLO or 2XLO is available on these pins.
VCO Control Voltage Input: This pin is driven by the output of the loop filter. Nominal input voltage range on this
pin is 1.5 V to 2.5 V
Exposed Paddle: The exposed paddle should be soldered to a low impedance ground plane.
When internal LO generation is disabled, an external 1XLO or 2XLO can be applied to these pins.
SET
is required. If DB18 is set to 1, the four nominal charge pump currents (I
LON/LOP Function
CP,BASE
Output (1XLO)
Output (1XLO)
Output (2XLO)
Output (2XLO)
Input (2XLO)
is the base charge pump current in μA. For further details on the charge pump current, see Register 4
R
SET
Table 5. Pin Function Descriptions
[ ]
Ω =
ENOP
0
1
⎡
⎢
⎣
X
LOSEL
Rev. PrE | Page 7 of 18
217 .4
0
X
X
1
1
250
×
I
CP BASE
R5:DB3 (LDRV)
,
TUNE
R5:DB6
X
X
X
0
1
1
0
1
through loop filter
⎤
⎥ −
⎦
37 .8
R5:DB5(LDIV)
DISABLED
DISABLED
NOMINAL
ENABLED
Output
X
0
0
1
1
) can be externally tweaked
R5:DB4(LXL)
1
X
X
X
X
ADRF6702