CD4017BMS Intersil Corporation, CD4017BMS Datasheet
CD4017BMS
Related parts for CD4017BMS
CD4017BMS Summary of contents
Page 1
... Each decoded output remains high for one full clock cycle. A CARRY- OUT signal completes one cycle every 10 clock input cycles in the CD4017BMS or every 8 clock input cycles in the CD4022BMS and is used to ripple-clock the succeeding device in a multi-device counting chain. ...
Page 2
... VDD = 15V, VOH > 13.5V, (Note 2) VOL < 1.5V NOTES: 1. All voltages referenced to device GND, 100% testing being im- plemented. 2. Go/No Go test with limits applied to inputs 2 CD4017BMS, CD4022BMS Reliability Information Thermal Resistance Ceramic DIP and FRIT Package . . . . Flatpack Package . . . . . . . . . . . . . . . . 10mA Maximum Package Power Dissipation (PD) at +125 ...
Page 3
... IOH15 Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < CD4017BMS, CD4022BMS GROUP A CONDITIONS (Note 1, 2) SUBGROUPS VDD = 5V, VIN = VDD or GND 10, 11 VDD = 5V, VIN = VDD or GND 10, 11 VDD = 5V, VIN = VDD or GND ...
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... NOTES: 1. All voltages referenced to device GND 50pF 200K, Input TR, TF < 20ns. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) 4 CD4017BMS, CD4022BMS CONDITIONS NOTES VDD = 10V VDD = 15V VDD = 10V ...
Page 5
... Subgroup B-5 Subgroup B-6 Group D NOTE Parameteric, 3% Functional; Cumulative for Static 1 and 2. CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN PART NUMBER CD4017BMS AND CD4002B Static Burn- Note 1 Static Burn- Note 1 Dynamic Burn Note 1 ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6 CD4017BMS, CD4022BMS FIGURE 1. CD4017BMS VDD VSS CARRY OUT 12 ...
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... CARRY OUT FIGURE 3. CD4017BMS 7 CD4017BMS, CD4022BMS All Inputs Protected by CMOS Protection Network FIGURE 2. CD4022BMS CLOCK ...
Page 8
... FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE ( +25 A 200 SUPPLY VOLTAGE (VDD 150 100 LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 8 CD4017BMS, CD4022BMS 12.5 10 7.5 2.5 15 FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT - AMBIENT TEMPERATURE (T -5 -10 -15 -20 -25 -30 FIGURE 8 ...
Page 9
... S-R flip-flop (constructed from two NOR gates of the CD4001B) generates a reset pulse which clears the CD4017BMS or CD4022BMS to its zero count. At this time, if the N output is greater than or equal the CD4017BMS the CD4022BMS, the C line goes high to clock the next OUT CD4017BMS or CD4022BMS counter section. The “ ...
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... Chip Dimensions and Pad Layouts METALLIZATION: Thickness: 11k PASSIVATION: 10.4kÅ - 15.6k BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 10 CD4017BMS, CD4022BMS CD4017BMSH Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions -3 as indicated. Grid graduations are in mils (10 ...