ACS8530 Semtech Corporation, ACS8530 Datasheet - Page 126

• Manufacturer Part Number: ACS8530
• Description: Synchronous Equipment Timing Source For Stratum 2/3E/3 Systems
• Manufacturer: Semtech Corporation

Address (hex):
Revision 3.01/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
ip_noise_
window
Bit No.
Bit 7
[3:0]
5
4
76 (cont...)
cnfg_phasemon
Description
phasemon_en
Register bit to enable the phase transient monitor,
which monitors the phase error between the output
of the DPLL and the reference input. With a low
bandwidth setting, a phase transient on the input
will be measured as a phase error by the phase
transient monitor. As the DPLL tracks the input
phase, this error will reduce as the phase is pulled
in. If this measured error is beyond the limit
specified in Bits [3:0] phasemon_limit, then a phase
monitor alarm will be raised.
phmon_PBO_en
Register bit to enable a phase transient monitor
alarm to automatically trigger a Phase Build-out
event.
phasemon_limit
Register to set the limit for the phase transient
monitor. Although this limit is set in microseconds,
the actual phase transient required to trigger the
alarm limit will depend on the rate of change of the
input phase and the bandwidth of the DPLL. With a
very low bandwidth and a relatively fast input phase
transient, the alarm will be triggered close to the
programmed limit. With a slower phase transient or
a higher bandwidth, the actual phase transient
required to trigger the alarm will be much greater.
This is because the monitor’s reference is taken
from the output of the DPLL and the phase error
measured will always be reduced as the DPLL
tracks the input phase.
Bit 6
phasemon_en
Bit 5
Description
phmon_PBO_
en
Bit 4
FINAL
Page 126
(R/W) Register to configure the
noise rejection function for low
frequency inputs.
Bit Value
Bit 3
0
1
0
1
-
Value Description
Phase transient monitor disabled.
Phase transient monitor enabled.
Phase transient alarm will not trigger PBO.
Phase transient alarm will trigger PBO.
This 4-bit unsigned integer represents the amount
of phase error required across the DPLL to cause
the phase transient alarm, Reg. 08 Bit 5. The phase
transient limit in time can be calculated by adding 7
to the value in the register, and multiplying by
156.25 ns. This gives a range of 1094 ns to
3437 ns.
Bit 2
phasemon_limit
Default Value
ACS8530 SETS
Bit 1
DATASHEET
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0000 0110
Bit 0