ACS8530 Semtech Corporation, ACS8530 Datasheet - Page 17

• Manufacturer Part Number: ACS8530
• Description: Synchronous Equipment Timing Source For Stratum 2/3E/3 Systems
• Manufacturer: Semtech Corporation

application) external software will be required to force the
device into Locked mode until phase lock has been
achieved. Without software control, if the device cannot
achieve lock within 100 seconds, the reference is
disqualified and a phase alarm is raised on it. The device
will then revert to Free-run mode and another reference
source, if available, will be selected.
Locked Mode
The Locked mode is entered from Pre-locked, Pre-locked2
or Phase-lost mode when an input reference source has
been selected and the DPLL has locked. The DPLL is
considered to be locked when the phase loss/lock
detectors (See“Phase Lock/Loss Detection” on page 21)
indicate that the DPLL has remained in phase lock
continuously for at least one second. When the ACS8530
is in Locked mode, the output frequency and phase tracks
that of the selected input reference source.
Lost-phase Mode
Lost-phase mode is used whenever the phase loss/lock
detectors (See“Phase Lock/Loss Detection” on page 21)
indicate that the DPLL has lost phase lock. The DPLL will
still be trying to lock to the input clock reference, if it
exists. If the Leaky Bucket Accumulator calculates that
the anomaly is serious, the device disqualifies the
reference source. If the device spends more than 100
seconds in Lost-phase mode, the reference is disqualified
and a phase alarm is raised on it. If the reference is
disqualified, one of the following transitions takes place:
1. Go to Pre-locked2;
2. Go to Holdover;
Holdover Mode
Holdover mode is the operating condition the device
enters when its currently selected input source becomes
invalid, and no other valid replacement source is
available. In this mode, the device resorts to using stored
frequency data, acquired when the input reference source
was still valid, to control its output frequency.
In Holdover mode, the ACS8530 provides the timing and
synchronization signals to maintain the Network Element
but is not phase locked to any input reference source. Its
output frequency is determined by an averaged version of
the DPLL frequency when last in the Locked Mode.
Revision 3.01/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
- If a known good stand-by source is available.
- If no stand-by sources are available.
FINAL
Page 17
Holdover can be configured to operate in either:
Automatic Mode
In Automatic mode, the device can be configured to
operate using either:
Averaged
In the Averaged mode, the frequency (as reported by
sts_current_DPLL_frequency, see Reg. 0C, Reg. 0D and
Reg. 07) is filtered internally using an Infinite Impulse
Response filter, which can be set to either:
Instantaneous
In Instantaneous mode, the DPLL freezes at the frequency
it was operating at the time of entering Holdover mode. It
does this by using only its internal DPLL integral path
value (as reported in Reg. 0C, 0D, and 07) to determine
output frequency. The DPLL proportional path is not used
so that any recent phase disturbances have a minimal
effect on the Holdover frequency. The integral value used
can be viewed as a filtered version of the locked output
frequency over a short period of time. The period being in
inverse proportion to the DPLL bandwidth setting.
Automatic Mode
(Reg. 34 Bit 4, cnfg_input_mode: man_holdover set
Low), or
Manual Mode
(Reg. 34 Bit 4, cnfg_input_mode: man_holdover set
High).
Averaged
(Reg. 40 Bit 7, cnfg_holdover_modes,
auto_averaging: set High) or
Instantaneous
(Reg. 40 Bit 7, cnfg_holdover_modes,
auto_averaging: set Low).
Fast
(Reg. 40 Bit 6, cnfg_holdover_modes, fast_averaging:
set High),
giving a -3 dB filter response point corresponding to a
period of approx. eight minutes, or
Slow
(Reg. 40 Bit 6, cnfg_holdover_modes, fast_averaging:
set Low)
giving a -3 dB filter response point corresponding to a
period of approx. 110 minutes.
ACS8530 SETS
DATASHEET
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