ACS8530 Semtech Corporation, ACS8530 Datasheet - Page 8

• Manufacturer Part Number: ACS8530
• Description: Synchronous Equipment Timing Source For Stratum 2/3E/3 Systems
• Manufacturer: Semtech Corporation

The ACS8530 is a highly integrated, single-chip solution
for the SETS function in a SONET/SDH Network Element,
for the generation of SEC and Frame/MultiFrame
Synchronization pulses. Digital Phase Locked Loop (DPLL)
and direct digital synthesis methods are used in the
device so that the overall PLL characteristics are very
stable and consistent compared to traditional analog
PLLs.
In Free-run mode, the ACS8530 generates a stable, low-
noise clock signal at a frequency to the same accuracy as
the external oscillator, or it can be made more accurate
via software calibration to within ±0.02 ppm. In Locked
mode, the ACS8530 selects the most appropriate input
reference source and generates a stable, low-noise clock
signal locked to the selected reference. In Holdover mode,
the ACS8530 generates a stable, low-noise clock signal,
adjusted to match the last known good frequency of the
last selected reference source. A high level of phase and
frequency accuracy is made possible by an internal
resolution of up to 54 bits and internal Holdover accuracy
of up to 7.5 x 10
frequency accuracy, jitter and drift performance of the
clock meet the requirements of ITU G.736
G783
Telcordia GR-253-CORE
The ACS8530 supports all three types of reference clock
source: recovered line clock, PDH network
synchronization timing and node synchronization. The
ACS8530 generates independent T0 and T4 clocks, an
8 kHz Frame Synchronization clock and a 2 kHz Multi-
Frame Synchronization clock.
One key architectural advantage that the ACS8530 has
over traditional solutions is in the use of DPLL technology
for precise and repeatable performance over temperature
or voltage variations and between parts. The overall PLL
bandwidth, loop damping, pull-in range and frequency
accuracy are all determined by digital parameters that
provide a consistent level of performance. An Analog PLL
(APLL) takes the signal from the DPLL output and provides
a lower jitter output. The APLL bandwidth is set four orders
of magnitude higher than the DPLL bandwidth. This
ensures that the overall system performance still
maintains the advantage of consistent behavior provided
by the digital approach.
The DPLLs are clocked by the external Oscillator module
(OCXO) so that the Free-run or Holdover frequency
stability is only determined by the stability of the external
Revision 3.01/October 2003 © Semtech Corp.
Introduction
ADVANCED COMMUNICATIONS
[9]
, G.812
[10]
-14
, G.813
(instantaneous). In all modes, the
[17]
[11]
and GR-1244-CORE
, G.823
[13]
, G.824
[7]
, G.742
[19]
[14]
.
[8]
and
,
FINAL
Page 8
oscillator module. This second key advantage confines all
temperature critical components to one well defined and
pre-calibrated module, whose performance can be
chosen to match the application; for example an OCXO for
Stratum 3E applications.
All performance parameters of the DPLLs are
programmable without the need to understand detailed
PLL equations. Bandwidth, damping factor and lock range
can all be set directly, for example. The PLL bandwidth
can be set over a wide range, 0.5 mHz to 70 Hz in 18
steps, to cover all SONET/SDH clock synchronization
applications.
The ACS8530 supports protection. Two ACS8530 devices
can be configured to provide protection against a single
ACS8530 failure. The protection maintains alignment of
the two ACS8530 devices (Master and Slave) and
ensures that both ACS8530 devices maintain the same
priority table, choose the same reference input and
generate the T0 clock, the 8 kHz Frame Synchronization
clock and the 2 kHz Multi-Frame Synchronization clock
with the same phase. The ACS8530 includes a multi-
standard microprocessor port, providing access to the
configuration and status registers for device setup and
monitoring.
Overview
The following description refers to the Block Diagram
(Figure 1 on page 1).
The ACS8530 SETS device has 14 input clocks, generates
11 output clocks, and has a total of 55 possible output
frequencies. There are two main paths through the
device: T0 and T4. Each path has an independent DPLL
and APLL pair.
The T0 path is a high quality, highly configurable path
designed to provide features necessary for node timing
synchronization within a SONET/SDH network. The T4
path is a simpler and less configurable path designed to
give a totally independent path for internal equipment
synchronization. The device supports use of either or both
paths, either locked together or independent.
Of the 14 input references, two are AMI composite clock,
two are LVDS/PECL and the remaining ten are TTL/CMOS
compatible inputs. All the TTL/CMOS are 3 V and 5 V
compatible (with clamping if required by connecting the
General Description
ACS8530 SETS
DATASHEET
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