ACS8530 Semtech Corporation, ACS8530 Datasheet - Page 26

• Manufacturer Part Number: ACS8530
• Description: Synchronous Equipment Timing Source For Stratum 2/3E/3 Systems
• Manufacturer: Semtech Corporation

phase shifts within the 0.1 second period operates in the
following manner: When the input phase changes by more
than 156 ns with respect to an internal version of the
DPLL output then the internal 0.1 second interval counter
is started. This internal DPLL output can be considered as
representing the previous phase of the input. If the phase
change is greater than the preset threshold
(programmable from 1 to 3.5 µs) during any time up to the
0.1 second limit, then a PBO event will be triggered
automatically (with Reg. 76, Bits 5 and 4 = 1), hence
absorbing the phase disturbance. The disturbance to the
DPLL is minimal with low DPLL bandwidth and when the
input phase change occurs within a small time interval.
When a PBO event is triggered, the device enters a
temporary Holdover state. When in this temporary state,
the phase of the input reference is measured, relative to
the output. The device then automatically accounts for
any measured phase difference and adds the appropriate
phase offset into the DPLL to compensate. Following a
PBO event, whatever the phase difference on change of
input, the output phase transient is minimized to be no
greater than 5 ns.
On the ACS8530, PBO can be enabled, disabled or frozen
using the microprocessor interface. By default, it is
enabled. When PBO is enabled, PBO can also be frozen (at
the current offset setting). The device will then ignore any
further PBO events occurring on any subsequent
reference switch, and maintain the current phase offset.
If PBO is disabled while the device is in the Locked mode,
there may be a phase shift on the output SEC clocks as
the DPLL locks back to 0 degrees phase error. The rate of
phase shift will depend on the programmed bandwidth.
Enabling PBO whilst in the Locked stated will also trigger
a PBO event.
PBO Phase Offset
In order to minimize the systematic (average) phase error
for PBO, a PBO Phase Offset can be programmed in
0.101 ns steps in the cnfg_PBO_phase_offset register,
Reg.72. The range of the programmable PBO phase offset
is restricted to ±1.4 ns. This can be used to eliminate an
accumulation of phase shifts in one direction.
Input to Output Phase Adjustment
When PBO is off (including Auto-PBO on phase transients),
such that the system always tries to align the outputs to
the inputs at the 0° position, there is a mechanism
provided in the ACS8530 for precise fine tuning of the
output phase position with respect to the input. This can
Revision 3.01/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 26
be used to compensate for circuit and board wiring
delays. The output phase can be adjusted in 6 ps steps up
to 200 ns in a positive or negative direction. The phase
adjustment actually changes the phase position of the
feedback clock so that the DPLL adjusts the output clock
phases to compensate. The rate of change of phase is
therefore related to the DPLL bandwidth. For the DPLL to
track large instant changes in phase, either Lock8k mode
should be on, or the coarse phase detector should be
enabled. Register cnfg_phase_offset at Reg. 70 and 71
controls the output phase, which is only used when PBO is
off (Reg. 48, Bit 2 = 0 and Reg. 76, Bit 4 = 0).
Input Wander and Jitter Tolerance
The ACS8530 is compliant to the requirements of all
relevant standards, principally ITU Recommendation
G.825
GR253
(1996)
All reference clock inputs have a tight frequency tolerance
but a generous jitter tolerance. Pull-in, hold-in and pull-out
ranges are specified in Table 7. Minimum jitter tolerance
masks are specified in Figures 9 and 10, and Tables 7
and 9, respectively. The ACS8530 will tolerate wander
and jitter components greater than those shown in
Figure 9 and Figure 10, up to a limit determined by a
combination of the apparent long-term frequency offset
caused by wander and the eye-closure caused by jitter
(the input source will be rejected if the offset pushes the
frequency outside the hold-in range for long enough to be
detected, whilst the signal will also be rejected if the eye
closes sufficiently to affect the signal purity). Either the
Lock8k mode, or one of the extended phase capture
ranges should be engaged for high jitter tolerance
according to these masks.
All reference clock ports are monitored for quality,
including frequency offset and general activity. Single
short-term interruptions in selected reference clocks may
not cause re- arrangements, whilst longer interruptions,
or multiple, short-term interruptions, will cause re-
arrangements, as will frequency offsets which are
sufficiently large or sufficiently long to cause loss-of-lock
in the phase-locked loop. The failed reference source will
be removed from the priority table and declared as
unserviceable, until its perceived quality has been
restored to an acceptable level.
[15]
[4]
[17]
.
, ANSI DS1.101-1999
, G812
[10]
, G813
[11]
ACS8530 SETS
[1]
and ETS 300 462-5
, Telcordia GR1244
DATASHEET
www.semtech.com
[19]
,