ACS8530 Semtech Corporation, ACS8530 Datasheet - Page 54

• Manufacturer Part Number: ACS8530
• Description: Synchronous Equipment Timing Source For Stratum 2/3E/3 Systems
• Manufacturer: Semtech Corporation

Table 29 Register Map
Revision 3.01/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
RO = Read Only
R/W = Read/Write
chip_id (RO)
chip_revision (RO)
test_register1 (R/W)
sts_interrupts (R/W)
sts_current_DPLL_frequency, see
OC/OD
sts_interrupts (R/W)
sts_operating (RO)
sts_priority_table (RO)
sts_current_DPLL_frequency[7:0] 0C 00
sts_sources_valid (RO)
sts_reference_sources (RO)
cnfg_ref_selection_priority (1 & 2) 18 32
(R/W)
cnfg_ref_source_frequency
cnfg_sts_remote_sources_valid
(R/W)
cnfg_operating_mode (R/W)
force_select_reference_source
(R/W)
(RO)
(R/W)
Status of Input pairs (1 & 2) 10 66
Register Name
(11 & 12) 15 66
(13 & 14) 16 66
(11 & 12) 1D DC
(13 & 14) 1E
(9 & 10) 14 66
(9 & 10) 1C BA
[18:16] 07 00
(3 & 4) 11 66
(5 & 6) 12 66
(7 & 8) 13 66
(3 & 4) 19 54
(5 & 6) 1A
(7 & 8) 1B 98
[15:8] 0D 00
_1 20 00
_2 21 00
10 29 03 divn_10
11 2A
12 2B 01 divn_12
13 2C 01 divn_13
14 2D 01 divn_14
3 22 00 divn_3
4 23 00 divn_4
5 24 03 divn_5
6 25 03 divn_6
7 26 03 divn_7
8 27 03 divn_8
9 28 03 divn_9
00 52
01 21
02 00
03 14 phase_alarm
05 FF
06 3F
07 00
08 50 Sync_ip_alarm T4_status
09 41 SYNC2K_
0B 00
0E
0F
30 FF
31 3F
32 00
33 0F
0A
00
00 I8
00
76
FE
03 divn_11
I8 valid
change
operating_
mode
alarm
Out-of-band
alarm (soft)
7 (MSB)
Set to zero
Set to zero
3rd highest priority validated source
disable_180
I7 valid
change
main_ref_
failed
T4_DPLL_lock
Highest priority validated source
I7
Out-of band
alarm (hard)
lock8k_3
lock8k_4
lock8k_5
lock8k_6
lock8k_7
lock8k_8
lock8k_9
lock8k_10
lock8k_11
lock8k_12
lock8k_13
lock8k_14
programmed_priority I10
programmed_priority I12
programmed_priority I14
programmed_priority I2
programmed_priority I4
programmed_priority I6
programmed_priority I8
Status of I10 Input
Status of I12 Input
Status of I14 Input
6
Status of I2 Input
Status of I4 Input
Status of I6 Input
Status of I8 Input
I6 valid
change
I14 valid
change
alarm
TO_DPLL_freq
_soft_alarm
I6
I14
No Activity
alarm
phasemon_
Device part number [15:8] 8 most significant bits of the chip ID
Device part number [7:0] 8 least significant bits of the chip ID
FINAL
Page 54
5
bucket_id_10
bucket_id_11
bucket_id_12
bucket_id_13
bucket_id_14
bucket_id_1
bucket_id_2
bucket_id_3
bucket_id_4
bucket_id_5
bucket_id_6
bucket_id_7
bucket_id_8
bucket_id_9
Bits [15:8] of current DPLL frequency
Bits [7:0] of current DPLL frequency
resync_
analog
I5 valid
change
I13 valid
change
T4_inputs_
failed
T4_DPLL_freq
_soft_alarm
I5
I13
Phase lock
alarm
Remote status, channels <8:1>
Chip revision number [7:0]
4
Data Bit
Remote status, channels <14:9>
Set to zero
I4 valid
change
I12 valid
change
AMI2_Viol
I4
I12
Out-of-band
alarm (soft)
3
2nd highest priority validated source
reference_source_frequency_10
reference_source_frequency_11
reference_source_frequency_12
reference_source_frequency_13
reference_source_frequency_14
I3
8K edge
polarity
I3 valid
change
I11 valid
change
Bits [18:16] of current DPLL frequency
AMI2_LOS
I11
Out-of band
alarm (hard)
reference_source_frequency_3
reference_source_frequency_4
reference_source_frequency_5
reference_source_frequency_6
reference_source_frequency_7
reference_source_frequency_8
reference_source_frequency_9
Currently selected source
programmed_priority I11
programmed_priority I13
forced_reference_source
programmed_priority I1
programmed_priority I3
programmed_priority I5
programmed_priority I7
programmed_priority I9
ACS8530 SETS
2
Status of I11 Input
Status of I13 Input
Bits [18:16] of current DPLL offset
Status of I3 Input
Status of I5 Input
Status of I7 Input
Status of I1 Input
Status of I9 Input
Set to zero
Set to zero
T0_DPLL_operating_mode
TO_DPLL_operating_mode
Set to zero
I2 valid
change
I10 valid
change
AMI1_Viol
I2
I10
No activity
alarm
1
DATASHEET
www.semtech.com
Set to zero
I1 valid
change
I9 valid
change
AMI1_LOS
I1
I9
Phase lock
alarm
0 (LSB)