SPC7283 Epson Electronics America, Inc., SPC7283 Datasheet
SPC7283
Related parts for SPC7283
SPC7283 Summary of contents
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MF1447 - 01 IEEE1394 Controller IEEE1394 Controller S1R75801F00A S1R72803F00A Technical Manual Technical Manual ...
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NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson ...
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The information of the product number change Starting April 1, 2001 the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative. Configuration ...
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DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. INTERNAL BLOCK DESCRIPTION .................................................................................................................. 3 3.1 BLOCK DIAGRAM ..................................................................................................................................... 3 3.2 BLOCK DIAGRAM DESCRIPTION ............................................................................................................ 3 4. INTERNAL CONNECTION DIAGRAM .............................................................................................................. 4 5. PIN ASSIGNMENT DIAGRAM .......................................................................................................................... 5 6. PIN DESCRIPTION ...
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DESCRIPTION The S1R72801F00A is a LINK/Transaction controller based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It integrates a built-in CPU and Flash ROM, and also integrates a part of transaction functions into hardware. If you set a PageTable ...
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S1R72803F00A Built-in CPU Integration of a CPU eliminated the necessity of an external CPU to control this IC. CPU core: 32-bit RISC CPU S1C33000 Harvard architecture (Concurrency of a fetch and load/store) High speed/high performance: Ready for operation with 25MHz ...
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INTERNAL BLOCK DESCRIPTION 3.1 BLOCK DIAGRAM HDD [15:0] HDMARQ XHIOR IDE XHIOW FIFO XHDMACK IDE HIORDY I/F HINTRQ XHPDIAG HDA [2:0] IDE XCS [1:0] DMA XHDASP XHRST Register for IDE EXCLK_EN OSC3 PLLS1 PLLS0 FLASH ROM 64KByte ICEMD (32KWord ...
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S1R72803F00A 4. INTERNAL CONNECTION DIAGRAM XRESET U_AD<23:0> AD<23:00> U_DT<15:0> xCSREG<XCE4> xCSBUF<XCE7> DT<15:00> xCSFREG<XCE5> xCSFLS<XCE10> XCE10EX XCE9 XCE8 xINT(K65) XCE6 SLEEP(P33) XRD XWRL XWRH C33 Core BCLK XNMI X2SPDX ICEMD DSIO OSC3 EXCLK_EN PLLC PLLS1 PLLS0 EA10MD2 EA10MD1 EA10MD0 4 U_AD<12:0> ...
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PIN ASSIGNMENT DIAGRAM LV 139 DD N.C. 140 P22 141 P23 142 K66 143 K67 144 XWAIT 145 P00 146 P01 147 V 148 SS P02 149 P03 150 P04 151 P05 152 P06 153 P07 154 X2SPDX 155 ...
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S1R72803F00A 6. PIN DESCRIPTION Control signals with an “X” as the first character of a pin name are low active. (Excluding X2SPD) Pin Name PIN I/O Reset 1394PHY interface ( Hi-Z (MSB Hi-Z ...
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Pin Name PIN I/O Reset IDE Interface ( HDA2 61 Otr Hi-Z (MSB) HDA1 64 Otr Hi-Z IDE Address Signal HDA0 62 Otr Hi-Z (LSB) XHCS1 59 Otr Hi-Z IDE Chip Select Signal XHCS0 60 Otr Hi-Z IDE ...
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S1R72803F00A Pin Name PIN I/O Reset C33 External Interface (HV P07 154 B P06 153 B P05 152 B P04 151 B SRDY(P03) 150 B SCLK(P02) 149 B SOUT(P01) 147 B SIN(P00) 146 B K67 144 I K66 143 I ...
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Pin Name PIN I/O Reset Other Pins ICEMD 179 I X2PSDX 155 I XNMI 177 I XRESET 178 I HCLK 181 O EXCLK_EN 116 I TVEP 58 – Test Pin TI8 121 I TO7 122 O TO6 123 O TO5 ...
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S1R72803F00A 7. FUNCTIONAL DESCRIPTION 7.1 MEMORY MAP 7.1.1 All Memory Space Area Address 0x000000 Area 0 0x002000 0x030000 Area 1 0x040000 0x050000 0x060000 Area 2 0x080000 Area 3 0x100000 Area 4 0x100080 0x200000 Area 5 0x200008 0x300000 Area 6 0x400000 ...
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IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM) 0x400000 0x4000C0 0x4000E0 0x400100 0x401FFF TxHeaderArea used Asyncronouse only TxAreaStart + 0x20 + 0x40 • All RAM areas are accessible from the CPU by direct addressing. • Hardware DMA is possible to the IDE ...
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S1R72803F00A 7.2 IEEE1394 PACKET FORMAT 7.2.1 Transmit Packet Format (1) TxAsyncronousePacket <3> QuadReadReq, WriteResp b. – 1 DestinationID QuadReadReq (tcode : 0x4) 1 DestinationID 2 2 WriteResp (tcode : 0x2) ...
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TxAsyncronousePacket <5> BlockWriteReq, BlockReadResp, LockReq, LockResp b. – 0 DestinationID 1 2 DataLength BlockWriteReq LockReq 1 DestinationID 2 2 BlockReadResp LockResp 1 DestinationID 2 (4) TxAsyncronousePhyPacket (tcode : 0xE) b.31 24 ...
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S1R72803F00A 7.2.2 Receive Packet Format (1) RxAsyncronousePacket <4> QuadReadReq, WriteResp b. – 0 DestinationID 1 2 SourceID QuadReadReq (tcode : 0x4) 2 SourceID 3 2 WriteResp (tcode : 0x2) 2 SourceID 3 ...
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RxAsyncronousePacket <6> BlockWriteReq, BlockReadResp, LockReq, LockResp b. – DestinationID 2 SourceID 3 DataLength BlockWriteReq (tcode : 0x1) LockReq (tcode : 0x9) 2 SourceID 3 2 BlockReadResp (tcode : 0x7) LockResp ...
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S1R72803F00A (6) RxIsocronousePacket (tcode : 0xA) b. – 1 DataLength Receive Packet Common Format b. – Name Bit count speed ...
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IEEE1394 HARDWARE SBP-2 CONTROL The hardware SBP2 of this IC automatically executes a PageTable fetch and data transfer according to the Serial Bus Protocol 2 after receiving specifications of its PageTable Size and Address. The control of the SBP2 ...
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S1R72803F00A 7.6 FLASH CONTROLLER This IC is provided with a function to perform Erase and Write to the Flash ROM. (1) Chip Erase According to a specified sequence, you can erase all memory cells in the built-in Flash ROM to ...
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INTERNAL REGISTER 8.1 IEEE1394 LINK CONTROLLER REGISTER MAPPING 8.1.1 Register Table (The base address of this register is 0x100000.) Address Register Name 0x00 MainIntStat 0x01 SubIntStat 0x02 (Reserved) 0x03 DmaIntStat 0x04 LinkIntStat1 0x05 LinkIntStat0 0x06 PhyIntStat 0x07 (Reserved) 0x08 ...
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S1R72803F00A Address Register Name 0x2D CYCLE_TIME_MH 0x2E CYCLE_TIME_ML 0x2F CYCLE_TIME_L 0x30 HwSBP2Ctl 0x31 HwSBP2Stat 0x32 HwSBP2IntStat 0x33 HwSBP2Index 0x34 HwSBP2Window_H 0x35 HwSBP2Window_L 0x36 PayloadSize_H 0x37 PayloadSize_L 0x38 PageTableSize_H 0x39 PageTableSize_L 0x3A PageTableAdrs0 0x3B PageTableAdrs1 0x3C PageTableAdrs2 0x3D PaqeTableAdrs3 0x3E PageTableAdrs4 ...
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Address Register Name 0x60 IDE_Config0 0x61 IDE_Config1 0x62 IDE_RegAccCyc 0x63 IDE_PioDmaCyc 0x64 IDE_UltraDmaCyc 0x65 IDE_DmaCtl 0x66 IDE_BusStat 0x67 IDE_DmaStat 0x68 IDE_ByteCount0 0x69 IDE_ByteCount1 0x6A IDE_ByteCount2 0x6B IDE_ByteCount3 0x6C IDE_CRC0 0x6D IDE_CRC1 0x6E (Reserved) 0x6F (Reserved) 0x70 IDE_CS00 0x71 IDE_CS01 0x72 ...
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S1R72803F00A 8.1.2 Register/Bit Table The base address of this register is 0x100000. Address Register Name bit7 0x00 MainIntStat SubIntStat 0x01 SubIntStat SelfIDdone 0x02 (Reserved) 0x03 DmaIntStat 0x04 LinkIntStat1 0x05 LinkIntStat0 UnExpCh 0x06 PhyIntStat SubGap 0x07 (Reserved) 0x08 MainIntEnb EnSubIntStat EnTxIsoCmp ...
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Address Register Name bit7 0x30 HwSBP2Ctl PtNotPresen 0x31 HwSBP2Stat FwPause 0x32 HwSBP2IntStat SplitTimeOut TxAckedIlleg 0x33 HwSBP2Index 0x34 HwSBP2Window_H (MSB) 0x35 HwSBP2Window_L 0x36 PayloadSize_H (MSB) 0x37 PayloadSize_L 0x38 PageTableSize_H (MSB) 0x39 PageTableSize_L 0x3A PageTableAdrs0 (MSB) 0x3B PageTableAdrs1 0x3C PageTableAdrs2 0x3D PaqeTableAdrs3 ...
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S1R72803F00A Address Register Name bit7 0x60 IDE_Config0 UltraDmaMode DmaMode 0x61 IDE_Config1 IDE_Reset 0x62 IDE_RegAccCyc 0x63 IDE_PioDmaCyc 0x64 IDE_UltraDmaCyc 0x65 IDE_DmaCtl 0x66 IDE_BusStat DMARQ 0x67 IDE_DmaStat 0x68 IDE_ByteCount0 (MSB) 0x69 IDE_ByteCount1 0x6A IDE_ByteCount2 0x6B IDE_ByteCount3 0x6C IDE_CRC0 (MSB) 0x6D IDE_CRC1 0x6E ...
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Compare Address Index/Window Register CmprIndex ChnlWindow bit7 0x00 CompareDOffset0 (MSB) 0x01 CompareDOffset1 0x02 CompareDOffset2 0x03 CompareDOffset3 0x04 CompareDOffset4 0x05 CompareDOffset5 0x06 (Reserved) : (Reserved) 0x0F (Reserved) H/W SBP2 Index Chnnel/Window Register SBP2Index SBP2Window_H/L bit7 0x00 PageBoundary PageElementNunber 0x01 PgElmentRemain_H (MSB) ...
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S1R72803F00A 8.1.3 Register Map (The base address of this register is 0x100000.) Address Register Name Bit Symbol 0x00 MainIntStat 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp 2: IDE_DmaCmp 1: IDE_INTRQ 0: BusReset 0x01 SubIntStat 7: SelfIDdone 6: SelfIDerr ...
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Address Register Name Bit Symbol 0x08 MainIntEnb 7: EnSubIntStat 6: EnTxIsoCmp 5: EnRxDmaCmp 4: EnTxAsyCmp 3: EnHwSBP2Cmp 2: EnIDE_DmaCmp 1: EnIDE_INTRQ 0: EnBusReset 0x09 SubIntEnb 7: EnSelfIDdone 6: EnSelfIDerr 5: EnHwSBP2Err 4: EnHwSBP2BRst 3: EnLinkIntStat1 2: EnLinkIntStat0 1: EnPhyIntStat 0: ...
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S1R72803F00A Address Register Name Bit Symbol 0x10 ChipCtl 7: Suspend IDE_MdlRst 1: SendTardy 0: SoftReset 0x11 HW_Revision 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] 0x12 (Reserved) ...
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Address Register Name Bit Symbol 0x18 LinkCtl_H 7: PassSelfID 6: PassPhyPkt 5: PassBrPkt 4: EnPosWB 3: EnPosWQ 2: APHY 1: EnAcc 0: Cmstr 0x19 LinkCtl_L 7: EnLink 6: 5: PLIFrst 4: IgnrBChdr 3: IgnrBCdata 2: RxBusyMode 1: DualRtyEnb 0: SinglRtyEnb ...
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S1R72803F00A Address Register Name Bit Symbol 0x20 NODE_IDS_H 7: BusID[9] 6: BusID[8] 5: BusID[7] 4: BusID[6] 3: BusID[5] 2: BusID[4] 1: BusID[3] 0: BusID[2] 0x21 NODE_IDS_L 7: BusID[1] 6: BusID[0] 5: PhyID[5] 4: PhyID[4] 3: PhyID[3] 2: PhyID[2] 1: PhyID[1] ...
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Address Register Name 0x28 ChnlIndex Channel Index[3] 2: Channel Index[2] 1: Channel Index[1] 0: Channel Index[0] 0x29 ChnlWindow 7: Channel Window[7] 6: Channel Window[6] 5: Channel Window[5] 4: Channel Window[4] 3: Channel Window[3] 2: Channel ...
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S1R72803F00A Address Register Name 0x30 HwSBP2Ctl 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: LastPT 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start 0x31 HwSBP2Stat 7: FwPause 6: ErrPause 5: NotQuadEnable 4: WaitPLReady 3: HwSBP2Exec 2: PTaskExec 1: StTaskExec 0: TranExec ...
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Address Register Name Bit Symbol 0x38 PageTableSize_H 7: Page Table Size[15] 6: Page Table Size[14] 5: Page Table Size[13] 4: Page Table Size[12] 3: Page Table Size[11] 2: Page Table Size[10] 1: Page Table Size[9] 0: Page Table Size[8] R/W ...
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S1R72803F00A Address Register Name Bit Symbol 0x40 LinkRxHdrPtr_H LRHP[12] 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] 0: LRHP[8] 0x41 LinkRxHdrPtr_L 7: LRHP[7] 6: LRHP[6] 5: LRHP[ 0x42 LinkRxORBPtr_H ...
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Address Register Name Bit Symbol 0x48 UsedRxHdrPtr_H URHP[12] 3: URHP[11] 2: URHP[10] 1: URHP[9] 0: URHP[8] 0x49 UsedRxHdrPtr_L 7: URHP[7] 6: URHP[6] 5: URHP[ 0x4A UsedRxORBPtr_H UOP[12] ...
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S1R72803F00A Address Register Name Bit Symbol 0x50 BufControl 7: TxStreamClr 6: RxStreamClr 5: RxORBClr 4: RxHdrClr UpdLinkTxStrm 0x51 BufMonitor 7: RxPayldRdy 6: TxPayldRdy 5: 4: TxStreamFull 3: RxHdrRemain 2: RxORBFull 1: RxStreamFull 0: RxHdrFull 0x52 AsyDmaCtl ...
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Address Register Name Bit Symbol 0x58 BRstHdrPtr_H BusResetPtr[12] 3: BusResetPtr[11] 2: BusResetPtr[10] 1: BusResetPtr[9] 0: BusResetPtr[8] 0x59 BRstHdrPtr_L 7: BusResetPtr[7] 6: BusResetPtr[6] 5: BusResetPtr[ 0x5A BRstORBPtr_H BusRstORBPtr[12] ...
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S1R72803F00A Address Register Name Bit Symbol 0x60 IDE_Config0 7: UltraDmaMode 6: DmaMode 5: ActPort 4: IDE_Slave 3: DMARQ_Level 2: Swap 1: 0: 0x61 IDE_Config1 7: IDE_Reset XDIOW_DLYen R 0x62 IDE_RegAccCyc 7: Assert Pulse[3] ...
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Address Register Name Bit Symbol 0x68 IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] 0x69 IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 3: ByteCount[19] 2: ByteCount[18] 1: ByteCount[17] 0: ...
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S1R72803F00A Address Register Name Bit Symbol 0x70 IDE_CS00 0x71 IDE_CS01 0x72 IDE_CS02 0x73 IDE_CS03 7: 6: ...
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Address Register Name Bit Symbol 0x78 IDE_CS10 0x79 IDE_CS11 0x7A IDE_CS12 0x7B IDE_CS13 ...
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S1R72803F00A 8.1.4 Detail Description of Register (The base address of this register is 0x100000.) Address Register Name Bit Symbol 0x00 MainIntStat 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp R(W) 0: None 2: IDE_DmaCmp R(W) 0: None 1: IDE_INTRQ ...
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Address Register Name Bit Symbol 0x01 SubIntStat 7: SelfIDdone 6: SelfIDerr 5: HwSBP2Err 4: HwSBP2BRst R(W) 0: None 3: LinkIntStat1 2: LinkIntStat0 1: PhyIntStat 0: DmaIntStat Sub-Interrupt Status Register The value of each bit of this register indicates the status ...
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S1R72803F00A Address Register Name Bit Symbol 0x03 DmaIntStat 7: 6: TxAsyRtyGo 5: TxAsyBCSent R(W) 0: None 4: RxDmaFaild 3: TxAsyFaild 2: TxIsoFaild 1: TxAsyBRAbort R(W) 0: None 0: TxAsyMiss DMA Interrupt Status Register The value of each bit of this ...
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Address Register Name Bit Symbol 0x04 LinkIntStat1 RxOnTardy 2: RxHcrcErr 1: RxUnkTcode 0: TxRtyExced LINK Core Interrupt Status Register 1 The value of each bit of this register indicates the status of a corresponding interrupt ...
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S1R72803F00A Address Register Name Bit Symbol 0x05 LinkIntStat0 7: UnExpCh 6: DupliCh 5: IsoArbFaild 4: CycTooLong 3: CycOverFlw 2: CycEvent 1: CycLost 0: CycArbFail LINK Core Interrupt Status Register 0 The value of each bit of this register indicates the ...
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Address Register Name Bit Symbol 0x06 PhyIntStat 7: SubGap 6: ArbGap Phy_int 1: PhyWrDone 0: PhyRdDone PHY Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. ...
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S1R72803F00A Address Register Name Bit Symbol 0x08 MainIntEnb 7: EnSubIntStat 6: EnTxIsoCmp 5: EnRxDmaCmp 4: EnTxAsyCmp 3: EnHwSBP2Cmp 2: EnIDE_DmaCmp R/W 1: EnIDE_INTRQ 0: EnBusReset Main Interrupt Enable Flag Register This register enables/disables an interrupt factor of the MainIntStat Register. ...
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Address Register Name 0x0B DmaIntEnb 7: 6: EnTxAsyRtyGo 5: EnTxAsyBCSent 4: EnRxDmaFaild 3: EnTxAsyFaild 2: EnTxIsoFaild 1: EnTxAsyBRAbort 0: EnTxAsyMiss DMA Interrupt Enable Flag Register This register enables/disables an interrupt factor of the DMAIntStat Register. Setting the corresponding bit to ...
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S1R72803F00A Address Register Name Bit Symbol 0x0E PhyIntEnb 7: EnSubGap 6: EnArbGap EnPhy_int 1: EnPhyWrDone 0: EnPhyRdDone PHY Core Interrupt Enable Flag Register This register enables/disables an interrupt factor of the PHYIntStat Register. Setting the corresponding ...
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Address Register Name Bit Symbol 0x11 HW_Revision 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] Hardware Revision Register The HW_Revision Register indicates the revision number of a chip. Address Register Name Bit ...
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S1R72803F00A Address Register Name Bit Symbol 0x19 LinkCtl_L 7: EnLink 6: 5: PLIFrst 4: IgnrBChdr 3: IgnrBCdata 2: RxBusyMode 1: DualRtyEnb 0: SinglRtyEnb LINK Core Control Register Lower Rank This register controls the functions of the LINK core. Bit7 Enable ...
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Address Register Name Bit Symbol 0x1B PriReqCnt PriReq[5] 4: PriReq[4] 3: PriReq[3] 2: PriReq[2] 1: PriReq[1] 0: PriReq[0] Priority Request Count Register This register shows registers in the pri-req field shown in the PRIORITY_BUDGET(CSR) register. This register ...
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S1R72803F00A Address Register Name Bit Symbol 0x1E MaxRetry maxRty[3] 2: maxRty[2] 1: maxRty[1] 0: maxRty[0] Single Retry Limit Set Register This register sets the number of retries of the Single Phase Retry protocol. When its ...
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Address Register Name Bit Symbol 0x20 NODE_IDS_H 7: BusID[9] 6: BusID[8] 5: BusID[7] 4: BusID[6] 3: BusID[5] 2: BusID[4] 1: BusID[3] 0: BusID[2] 0x21 NODE_IDS_L 7: BusID[1] 6: BusID[0] 5: PhyID[5] 4: PhyID[4] 3: PhyID[3] 2: PhyID[2] 1: PhyID[1] 0: ...
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S1R72803F00A Address Register Name Bit Symbol 0x25 PhyAccCtl_L 7: WrDat[7] 6: WrDAt[6] 5: WrDat[5] 4: WrDat[4] 3: WrDat[3] 2: WrDat[2] 1: WrDat[1] 0: WrDat[0] PHY Register Access Control Register (Lower Rank) Bit7..0 PHY Write Data Set data to write to ...
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Address Register Name 0x28 ChnlIndex Channel Index[3] 2: Channel Index[2] 1: Channel Index[1] 0: Channel Index[0] 0x29 ChnlWindow 7: Channel Window[7] 6: Channel Window[6] 5: Channel Window[5] 4: Channel Window[4] 3: Channel Window[3] 2: Channel ...
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S1R72803F00A Address Register Name 0x2A CmprIndex Compare Index[3] 2: Compare Index[2] 1: Compare Index[1] 0: Compare Index[0] 0x2B CmprWindow 7: Compare Window[7] 6: Compare Window[6] 5: Compare Window[5] 4: Compare Window[4] 3: Compare Window[3] 2: ...
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Address Register Name 0x2C CYCLE_TIME_H 7: Cycle Second[6] 6: Cycle Second[5] 5: Cycle Second[4] 4: Cycle Second[3] 3: Cycle Second[2] 2: Cycle Second[1] 1: Cycle Second[0] 0: Cycle Count[12] 0x2D CYCLE_TIME_MH 7: Cycle Count[11] 6: Cycle Count[10] 5: Cycle Count[9] ...
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S1R72803F00A Address Register Name Bit Symbol 0x30 HwSBP2Ctl 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: LastPT 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start Hardware SBP2 Control Register This register controls the SBP2 processing of this IC. Bit7 UltraDmaMode PtNotPresent:0 ...
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Address Register Name Bit Symbol 0x31 SBP2Stat 7: FwPause 6: ErrPause 5: NotQuadEnable 4: WaitPLReady 3: HwSBP2Exec 2: PTaskExec 1: StTaskExec 0: TranExec Hardware SBP2 Status Read Register This register indicates the execution condition of the hardware SBP2. Bit7 F/W ...
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S1R72803F00A Address Register Name Bit Symbol 0x32 SBP2IntStat 7: SplitTimeOut 6: TxAckedIllegal R(W) 0: None 5: TxAckMiss 4: BrAbort 3: NotQuad 2: RxNotRespCmp R(W) 0: None 1: RxBroadCast R(W) 0: None 0: RxAckDataErr R(W) 0: None Hardware SBP2 Interrupt Status ...
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Address Register Name 0x33 HwSBP2Index 0x34 HwSBP2Window_H 7: HwSBP2 Window[15] 0x35 HwSBP2Window_L Hardware SBP2 Index Window Register This register functions as an Index Register and Window Register to set a register to use for the HwSBP2 processing. HwSBP2Index This register ...
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S1R72803F00A H/W SBP2 Index Chnnel/Window Register SBP2Index SBP2Window_H/L bit7 0x00 PageBoundary PageElementNunber 0x01 PgElmentRemain_H (MSB) PgElmentRemain_L 0x02 SpeedCode MaxPayload 0x03 DestinationID_H (MSB) DestinationID_L 0x04 SplitTime_H SplitTime_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) PageBoundary Set a value of page boundary to ...
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Address Register Name Bit Symbol 0x36 PayloadSize_H Payload Size[11] 2: Payload Size[10] 1: Payload Size[9] 0: Payload Size[8] 0x37 PayloadSize_L 7: Payload Size[7] 6: Payload Size[6] 5: Payload Size[5] 4: Payload Size[4] 3: Payload Size[3] ...
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S1R72803F00A Address Register Name Bit Symbol 0x3A PageTableAdrs0 7: PtAdress[47] 6: PtAdress[46] 5: PtAdress[45] 4: PtAdress[44] 3: PtAdress[43] 2: PtAdress[42] 1: PtAdress[41] 0: PtAdress[40] 0x3B PageTableAdrs1 7: PtAdress[39] 6: PtAdress[38] 5: PtAdress[37] 4: PtAdress[36] 3: PtAdress[35] 2: PtAdress[34] 1: PtAdress[33] ...
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Address Register Name Bit Symbol 0x40 LinkRxHdrPtr_H LRHP[12] 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] 0: LRHP[8] 0x41 LinkRxHdrPtr_L 7: LRHP[7] 6: LRHP[6] 5: LRHP[ Receive Header LINK Pointer Register This Receive ...
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S1R72803F00A Address Register Name Bit Symbol R/W 0x44 LinkRxStreamPtr_H PSP[12] 3: PSP[11] 2: PSP[10] 1: PSP[9] 0: PSP[8] 0x45 LinkRxStreamPtr_L 7: PSP[7] 6: PSP[6] 5: PSP[5] 4: PSP[4] 3: PSP[3] 2: PSP[ Receive Stream ...
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Address Register Name Bit Symbol R/W 0x48 UsedRxHdrPtr_H URHP[12] 3: URHP[11] 2: URHP[10] 1: URHP[9] R/W 0: URHP[8] 0x49 UsedRxHdrPtr_L 7: URHP[7] 6: URHP[6] 5: URHP[ Used Receive Header Pointer Register ...
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S1R72803F00A Address Register Name Bit Symbol R/W 0x4C IDE_RxStreamPtr_H IRSP[12] 3: IRSP[11] 2: IRSP[10] 1: IRSP[9] 0: IRSP[8] 0x4D IDE_RxStreamPtr_L 7: IRSP[7] 6: IRSP[6] 5: IRSP[5] 4: IRSP[4] 3: IRSP[3] 2: IRSP[ Receive Stream ...
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Address Register Name Bit Symbol 0x50 BufControl 7: TxStreamClr 6: RxStreamClr 5: RxORBClr 4: RxHdrClr UpdLinkTxStrm W Buffer Control Register This Buffer Control Register restores each pointer of the TxStreamArea, RxStreamArea, RxORBARea, and RxHeaderArea to the ...
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S1R72803F00A Address Register Name Bit Symbol 0x51 BufMonitor 7: RxPayldRdy 6: TxPayldRdy 5: 4: TxStreamFull 3: RxHdrRemain 2: RxORBFull 1: RxStreamFull 0: RxHdrFull Buffer Monitor Register This Buffer Monitor Register indicates each buffer area status. This register is read-only. Writing ...
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Address Register Name Bit Symbol 0x52 AsyDmaCtl 7: AsyChnlSel BlkWrAreaSel R ORB Area 3: AsyFIFOEpty R 2: AsyFIFOClr 1: AsyTxMon 0: AsyStart Async TxDMA Control Register Bit7 Async Transmit Packet Header Channel Select Selects the ...
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S1R72803F00A Address Register Name Bit Symbol 0x53 IsoDmaCtl 7: IsoChnlSel SelTxPtr 3: IsoFIFOEpty 2: IsoFIFOClr 1: IsoTxMon 0: IsoStart ISO TxDMA Control Register Bit7 ISO Transmit Packet Header Channel Select Selects the header area of an ISO ...
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Address Register Name Bit Symbol 0x54 RxDmaCtl RxFIFOEpty 2: RxFIFOClr 1: RxMon 0: ForceBusy Rx DMA Control Register Bit7..4 Reserved Bit3 Receive FIFO Empty When the DMA-FIFO for reception is empty, this bit becomes “0”. ...
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S1R72803F00A Address Register Name Bit Symbol 0x55 AreaIndex MemMapIndex[3] 2: MemMapIndex[2] 1: MemMapIndex[1] 0: MemMapIndex[0] 0x56 AreaWindow_H 7: MemMapWindow[15] 6: MemMapWindow[14] 5: MemMapWindow[13] 4: MemMapWindow[12] 3: MemMapWindow[11] 2: MemMapWindow[10] 1: MemMapWindow[9] 0: MemMapWindow[8] 0x57 AreaWindow_L ...
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Memory Map Area Index/Window Register AreaIndex AreaWindow_H/L bit7 0x00 RxORBAreaStart_H RxORBAreaStart_L 0x01 TxHdrAreaStart_H TxHdrAreaStart_L 0x02 TxStreamAreaStart_H TxStreamAreaStart_L 0x03 TxStreamAreaEnd_H TxStreamAreaEnd_L 0x04 RxStreamAreaStart_H RxStreamAreaStart_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) RxORBAreaStart This register sets the starting address of a receive ORB ...
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S1R72803F00A Address Register Name Bit Symbol 0x5A BRstORBPtr_H BusRstORBPtr[12] 3: BusRstORBPtr[11] 2: BusRstORBPtr[10] 1: BusRstORBPtr[9] 0: BusRstORBPtr[8] 0x5B BRstORBPtr_L 7: BusRstORBPtr[7] 6: BusRstORBPtr[6] 5: BusRstORBPtr[5] 4: BusRstORBPtr[4] 3: BusRstORBPtr[3] 2: BusRstORBPtr[ Bus Reset ORB ...
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Address Register Name Bit Symbol 0x5F MaintCtl_L 7: Ack[7] 6: Ack[6] 5: Ack[5] 4: Ack[4] 3: Ack[3] 2: Ack[2] 1: Ack[1] 0: Ack[0] Maintenance Control Register When the F_Ack bit is “1”, this register is enabled. When the F_Ack bit ...
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S1R72803F00A Address Register Name Bit Symbol 0x61 IDE_Config1 7: IDE_Reset XDIOW_DLYen R IDE Configuration Register This register sets the mode of operation of the IDE interface of this IC. Bit7 IDE_Reset Writing “1” ...
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Address Register Name Bit Symbol 0x63 IDE_PioDmaCyc 7: Assert Pulse[3] 6: Assert Pulse[2] R/W 5: Assert Pulse[1] 4: Assert Pulse[0] 3: Negate Pulse[3] 2: Negate Pulse[2] R/W 1: Negate Pulse[1] 0: Negate Pulse[0] IDE PIO/DMA Cycle Register This register sets ...
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S1R72803F00A Address Register Name Bit Symbol 0x65 IDE_DmaCtl IncFIFOCnt 4: CRC_Clear 3: FIFO_Clear 2: IDE_Abort 1: IDE_Direction 0: DmaStart IDE DMA Control Register This register makes control when transferring data through the IDE interface. Bit7..6 Reserved Bit5 ...
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Address Register Name Bit Symbol 0x67 IDE_DmaStat 7: FIFOCnt[2] 6: FIFOCnt[1] 5: FIFOCnt[ DmaPause 0: DmaRun IDE DMA Status Register This register indicates the status of the DMA of the IDE interface. Bit7::5 FIFOCnt[2:0] This bit ...
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S1R72803F00A Address Register Name Bit Symbol 0x68 IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] 0x69 IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 3: ByteCount[19] 2: ByteCount[18] 1: ByteCount[17] ...
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Address Register Name Bit Symbol 0x6C IDE_CRC0 7: CRC[15] 6: CRC[14] 5: CRC[13] 4: CRC[12] 3: CRC[11] 2: CRC[10] 1: CRC[9] 0: CRC[8] 0x6D IDE_CRC1 7: CRC[7] 6: CRC[6] 5: CRC[5] 4: CRC[4] 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: ...
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S1R72803F00A Address Register Name Bit Symbol 0x70 IDE_CS00 0x71 IDE_CS01 0x72 IDE_CS02 0x73 IDE_CS03 7: 6: ...
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Address Register Name 0x78 IDE_CS10 0x79 IDE_CS11 0x7A IDE_CS12 0x7B IDE_CS13 ...
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S1R72803F00A 8.2 FLASH ROM CONTROL REGISTER Address Register Name Bit Symbol 0x200000 FlashCtl 7: FlashCtlEnb Erase 3: FlashStat 2: FlashChipErs R/W 0: Chip All Erase Disable 1: FlashSctErs 0: FlashWrEnb Flash Control Register This register controls the ...
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Address Register Name Bit Symbol 0x200001 FlashCtlCnt_H FlashCtlCnt[21] 4: FlashCtlCnt[20] 3: FlashCtlCnt[19] 2: FlashCtlCnt[18] 1: FlashCtlCnt[17] 0: FlashCtlCnt[16] 0x200002 FlashCtlCnt_M 7: FlashCtlCnt[15] 6: FlashCtlCnt[14] 5: FlashCtlCnt[13] 4: FlashCtlCnt[12] R/W 3: FlashCtlCnt[11] 2: FlashCtlCnt[10] 1: FlashCtlCnt[9] 0: FlashCtlCnt[8] ...
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S1R72803F00A Address Register Name Bit Symbol 0x200004 FlashAdrs_H 7: Flash Address[15] 6: Flash Address[14] 5: Flash Address[13] 4: Flash Address[12] 3: Flash Address[11] 2: Flash Address[10] 1: Flash Address[9] 0: Flash Address[8] R/W When Data register's Low Byte is accessed, ...
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ELECTRICAL CHARACTERISTICS 9.1 ABSOLUTE MAXIMUM RATINGS Item Supply voltage Input voltage Output voltage Output current/pin Storage temperature 9.2 RECOMMENDED OPERATING CONDITION Item Supply voltage Input voltage Operating temperature Operating temperature when writing to FLASH ROM Symbol Rating HV –0.3 ...
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S1R72803F00A 9.3 DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) (1) Item Power supply current Power supply current Static current (Static current between HV Power supply current Static current (Static current between LV Power supply current Input leak Input leak current ...
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DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) (2) Item Output characteristics LOW level output voltage V HIGH level output voltage V Output characteristics OFF-STATE leak current I Input characteristics (Bus hold) LOW level HOLD current I HIGH level HOLD current ...
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S1R72803F00A 9.4 AC CHARACTERISTICS 9.4.1 Clock Timing 9.4.1.1 SCLK Timing SCLK 9.4.1.2 HCLK Timing HCLK Symbol T SCLK frequency 201 T SCLK duty cycle 202 T SCLK start 203 T HCLK frequency 204 T HCLK duty cycle 205 94 T ...
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PHY-LINK Interface Timing 9.4.2.1 Output timing SCLK Ctl[0:1] D[0:7] LReq 9.4.2.2 Input timing SCLK Ctl[0:1] D[0:7] LReq Symbol T SCLK rising edge 211 LReq delay time (Hi-Z T SCLK rising edge 212 LReq delay time (Outputting) T SCLK rising ...
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S1R72803F00A 9.4.3 IDE Interface Timing 9.4.3.1 PIO Read Direction of DATA Transfer XHCS0(O) HDA<2:0>(O) XHIOR(O) HDD<15:0>(O) XHIORDY(I) Symbol T XHCS0 321 HDA output delay time T XHCS0 HDA 322 HDA hold time T XHCS0 XHIOR 323 XHIOR set-up time T ...
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PIO Write Direction of DATA Transfer XHCS0(O) HDA<2:0>(O) XHIOW(O) HDD<15:0>(O) XHIORDY(I) Symbol T XHCS0 331 HDA output delay time T XHCS0 HDA 332 HDA hold time T XHCS0 333 XHIOW set-up time T XHIOW 334 XHIOW assert pulse width ...
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S1R72803F00A 9.4.3.3 DMA Read XHCS<1:0>(O) HDA<2:0>(O) HDMARQ(I) XHDAMCK(O) XHIOR(O) HDD<15:0>(I) Symbol T XHCS0,1 341 Address set-up time T XHIOR XHCS0,1 342 Address hold time T HDMARQ 343 XHDMACK response time T XHIOR HDMARQ negate 344 HDMARQ hold time T XHDMACK ...
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DMA Write XHCS<1:0>(O) HDA<2:0>(O) HDMARQ(I) XHDAMCK(O) XHIOW(O) HDD<15:0>(O) Symbol T XHCS0,1 351 Address set-up time T XHIOW 352 Address hold time T HDMARQ 353 XHDMACK response time T XHIOW 354 HDMARQ hold time T XHDMACK 355 XHIOR set-up time ...
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S1R72803F00A 9.4.3.5 Ultra-DMA Read Direction of DATA Transfer Initiating XHCS<1:0>(O) HDA<2:0>(O) HDMARQ(I) T362 XHDAMCK(O) XHIOW(O) (STOP) XHIOR(O) (HDMARDY) HIORDY(I) (DSTROBE) HDD<15:0>(I) Symbol T XHCS0,1 361 Address setup time T HDMARQ 362 XHDMACK response time T HDMACK 363 Envelope time T ...
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Direction of DATA Transfer Host Terminating XHCS<1:0>(O) HDA<2:0>(O) HDMARQ(I) T373 XHDAMCK(O) T371 XHIOW(O) (STOP) XHIOR(O) T372 (XHDMARDY) HIORDY(I) (DSTROBE) HDD<15:0>(O) (CRC) Symbol Specification T XHIOR XHIOW 371 Time before STOP is asserted T XHIOR HIORDY 372 Last strobe time T ...
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S1R72803F00A 9.4.3.6 Ultra-DMA Write Direction of DATA Transfer PORT XHCS<1:0>(O) HDA<2:0>(O) HDMARQ(I) XHDAMCK(O) XHIOW(O) (STOP) XHIOR(O) (HSTROBE) HIORDY(I) (XDDMARDY) HDD<15:0>(O) Symbol T XHCS0,1 381 Address setup time T HDMARQ 382 XHDMACK response time T HDMACK 384 Envelope time T XHIOW ...
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Direction of DATA Transfer Host Terminate XHCS<1:0>(O) HDA<2:0>(O) HDMARQ(I) XHDAMCK(O) T391 XHIOW(O) (STOP) HIORDY(I) (XDDMARDY) XHIOR(O) (HSTROBE) Data HDD<15:0>(O) Symbol T XHIOR XHIOW 391 Strobe stop time T HDMARQ 392 Constrained interlock time T XHIOR XHDMACK 393 Mimimum interlock time ...
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S1R72803F00A 9.4.4 CPU Interface Timing 9.4.4.1 CPU Read Cycle P_BCLK t AD P_A [23:0] P_CE X P_RD_X P_D[15:0] P_P30 (Wait input formulated according to the earliest signal change (Negate) among P_RD, P_CEx, P_A[23:0] RDH Symbol Specification t ...
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CPU Write Cycle P_BCLK t AD P_A[23:0] t CE1 P_CE X P_WR _X X P_D[15:0] t WTS P_P30 (Wait input) Symbol Specification t Address delay time AD t P_CEx delay time (1) CE1 t P_CEx delay time (2) CE2 ...
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S1R72803F00A 10. EXAMPLES OF EXTERNAL CONNECTION FOR REFERENCE PURPOSES 4.7K 17 10K R54 (H5) OPS 0.1u C37 ...
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R64 10K R63 10K R62 10K R61 10K R60 DD LV 139 N.C 140 TH3 TH P22 1 141 TH4 TH P23 1 142 K66 143 K67 144 XWAIT 145 CP2 CP P00 1 146 CP3 CP P01 1 ...
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S1R72803F00A HV DD R66 (2D5) XCE10EX HV DD R67 Note: The circuit of this sheet is an example of connection when an external ROM and SRAM are connected during the process of system development. This circuit is not required on ...
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SHAPE OF PACKAGE 139 184 Plastic QFP20-184 pin 22 –0.4 20 –0.1 138 INDEX 1 +0.05 0.4 0.16 —0.03 EPSON S1R72803F00A +0.05 0.125 —0.025 0¡ 10¡ 0.5 –0.2 1 109 ...
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In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings. ...
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S1R72803F00A Technical Manual This manual was made with recycle paper, and printed using soy-based inks. ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue September,2001 Printed in Japan H A ...