SPC7283 Epson Electronics America, Inc., SPC7283 Datasheet - Page 86

• Manufacturer Part Number: SPC7283
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72803F00A
IDE DMA Control Register
Bit7..6 Reserved
Bit5 IncFIFOCnt
Bit4 CRC_Clear
Bit3 FIFO_Clear
Bit2 IDE_Abort
Bit1 IDE_Direction
Bit0 DmaStart
IDE Bus Status Read Register
Bit7 DMARQ
Bit6 DMACK
Bit5 INTRQ
Bit4 IORDY
Bit3::2 Reserved
Bit1 DIAG
Bit0 DASP
82
Address Register Name
Address Register Name
0x65
0x66
This register makes control when transferring data through the IDE interface.
If DMA transfer is aborted, the data remained in the FIFO is discharged to the SRAM.
Operation:
1) Wait if FIFOCnt of the IDE_DmaStat register (0x67) is 3’b010 or higher.
2) When FIFOCnt becomes 3’b001, set IncFIFOCnt to 1 unless TxStreamFull of the BufMonitor register is full.
3) Abort the transfer when FIFOCnt becomes 3’b000.
Initializes the internal CRC calculation circuit. At start-up of the DMA, even the internal circuits are initialized
. Writing “1” to this bit clears the IDE_CRC0 and IDE_CRC1 Registers.
Clears the FIFO for IDE data transfer. Writing “1” to this bit clears the FIFO.
Use this bit to abort DMA data transfer in execution through the IDE interface. Writing “1” to this bit aborts
the DMA transfer.
Specifies a data flow direction for DMA data transfer in accordance with the IDE.
IDE_Direction:1 IDE -> SRAM (Buffer)
IDE_Direction:1 IDE <- SRAM (Buffer)
Setting this bit to “1” starts DMA transfer between the buffer and the IDE interface.
This register indicates the status of the signal of the IDE interface.
Indicates the state of the HDMARQ signal by positive logic.
(The status of the DMARQ_Level bit of the CONFIG0 is reflected.)
Indicates the state of the XHDMACK signal by positive logic.
Indicates the state of the HINTRQ signal by positive logic.
Indicates the state of the HIORDY signal by positive logic.
Indicates the state of the XHPDIAG signal by positive logic.
Indicates the state of the XHDASP signal by positive logic.
This bit causes FIFO counter increments to dump the data in the FIFO.
IDE_DmaCtl
IDE_BusStat
7:
6:
5: IncFIFOCnt
4: CRC_Clear
3: FIFO_Clear
2: IDE_Abort
1: IDE_Direction
0: DmaStart
7: DMARQ
6: DMACK
5: INTRQ
4: IORDY
3:
2:
1: DIAG
0: DASP
Bit Symbol
Bit Symbol
R/W
R
R/W
R/W
W
W
W
W
W
Indicate IDE I/F Signals State
EPSON
0:
0:
0: None
0: None
0: None
0: None
0: SRAM –> IDE 1: IDE –> SRAM
0: None
Description
Description
1:
1:
1: Push FIFO Data
1: CRC Clear
1: FIFO Clear
1: IDE Transfer Abort
1: IDE DMA Start
H.Rst S.Rst B.Rst
H.Rst S.Rst B.Rst
0x00 0x00
0x00 0x00
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–