SPC7283 Epson Electronics America, Inc., SPC7283 Datasheet - Page 85

• Manufacturer Part Number: SPC7283
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

IDE PIO/DMA Cycle Register
This register sets a transfer mode when transferring data through the IDE interface. It is enabled for an access to 0x70
Bit7::4 Asset Pulse
Bit3::0 Negate Pulse
IDE UltraDMA Cycle Register
Bit7::4 Assert Pulse
Bit3::0 Cycle Pulse
Address Register Name
Address Register Name
0x64
0x63
of the IDE-CSO Register.
It is common to both PIO/DMA modes.
Decides the minimum value of the assert period of the strobe signal when transferring data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Decides the minimum value of the negate period of the strobe signal when transferring data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Example: 0000: 2 x 20ns = 40ns
This register sets a transfer mode when transferring data by the Ultra-DMA through the IDE interface.
Decides the minimum value of the assert period of the strobe signal when transferring data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Decides the minimum cycle time of the strobe signal when transferring Ultra-DMA data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Example: 0000: 2 x 20ns = 40ns
IDE_PioDmaCyc 7: Assert Pulse[3]
IDE_UltraDmaCyc 7:
0001: 3 x 20s = 60ns
0001: 3 x 20s = 60ns
6: Assert Pulse[2] R/W
5: Assert Pulse[1]
4: Assert Pulse[0]
3: Negate Pulse[3]
2: Negate Pulse[2] R/W
1: Negate Pulse[1]
0: Negate Pulse[0]
6:
5:
4:
3: Cycle Time[3]
2: Cycle Time[2] R/W IDE Ultra DMA Transfer Mode Strobe Signal
1: Cycle Time[1]
0: Cycle Time[0]
Bit Symbol
Bit Symbol
R/W
R/W
0:
0:
0:
0:
Minimum Cycle Time
EPSON
IDE Transfer Mode Strobe Signal Assert Pulse
Width Minimum Value
IDE Transfer Mode Strobe Signal Negate Pulse
Width Minimum Value
Description
Description
1:
1:
1:
1:
H.Rst S.Rst B.Rst
H.Rst S.Rst B.Rst
S1R72803F00A
0x00 0x00
0x00
0x00
–
–
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