SPC7283 Epson Electronics America, Inc., SPC7283 Datasheet - Page 47

• Manufacturer Part Number: SPC7283
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

Sub-Interrupt Status Register
Bit7 Self Identify Period Complete
Bit6 Self Identify Packet Error
Bit5 HwSBP2Err
Bit4 BusReset in process HwSBP2
Bit3 LINK Core Interrupt Status1
Bit2 LINK Core Interrupt Status0
Bit1 PHY/LINK Interrupt Status
Bit0 LINK DMA Interrupt Status
Address Register Name
Address Register Name
0x01
0x02
The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become
“1” when the associated bit of the SubIntEnb Register is “1”, this register asserts an interrupt signal to the CPU.
The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read
value again, it clears these bits.
Subsequent to reading this register, the lower order 4 bits reads the Interrupt Status Register associated with each
bit to confirm which bit is an interrupt source and appropriately handle it. After that, it writes the read value
to the Interrupt Status Register to clear the bit. In the case that the interrupt factor still remains, however, the
bit is not cleared.
When a Self ID period finishes, this bit becomes “1”.
When a Self-ID packet with an error is received during the Self-ID period or when the Self-ID period finishes
due to an error, this bit becomes “1”.
When an interrupt factor from the HwSBP2 indicated on the HwSBP2IntStat Register exists, this bit becomes
“1”.
When a BusReset occurs in the HwSBP2 processing, this bit becomes “1”.
When an interrupt factor from the LINK core indicated on the LinkIntStat1 Register exists, this bit becomes “1”.
When an interrupt factor from the LINK core indicated on the LinkIntStat0 Register exists, this bit becomes “1”.
When an interrupt factor from the PHY status indicated on the PHYIntStat Register exists, this bit becomes “1”.
When an interrupt factor exists in the internal DMA operation indicated on the DmaIntStat Register, this bit
becomes “1”.
SubIntStat
(Reserved)
7: SelfIDdone
6: SelfIDerr
5: HwSBP2Err
4: HwSBP2BRst R(W) 0: None
3: LinkIntStat1
2: LinkIntStat0
1: PhyIntStat
0: DmaIntStat
7:
6:
5:
4:
3:
2:
1:
0:
Bit Symbol
Bit Symbol
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R/W
R/W
EPSON
0:
0:
0:
0:
0:
0:
0:
0:
1: Self-ID Phase Done
1: Self-ID Packet Error
1: Hw SBP2 Error
1: BusReset in process HwSBP
1: Link1 Interrupt Occurred
1: Link0 Interrupt Occurred
1: PHY Interrupt Occurred
1: Dma Interrupt Occurred
Description
Description
1:
1:
1:
1:
1:
1:
1:
1:
H.Rst S.Rst B.Rst
H.Rst S.Rst B.Rst
S1R72803F00A
0x00 0x00
0x00 0x00
–
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