MT92303 Zarlink Semiconductor, MT92303 Datasheet
MT92303
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MT92303 Summary of contents
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... Applications • Digital Telephone Sets • VoIP Enterprise Telephones G.712 Codec #1 Crosspoint G.712 Codec #0 VREF AUXTONE Figure 1 - Functional Block Diagram MT92303 Preliminary Information ISSUE 1 March 2000 Ordering Information 44 Pin MQFP -40 to +85° C EAR Audio Interface MIC #3 BIAS MICDET EAR Audio Interface ...
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... MT92303 DSTo/D /STD out DSTi/D /SRD in F0i/FSC/SC2 C4i/DCL/SCK SYSCLK VDDD GNDD DATA2 DATA1 SCLK Pin Description Pin # Name Type 5 SYSCLK Input Master clock (2.048, 4.096, 10.24, 20.0, 20.48, 25.0 or 50.0MHz) 12 RESETB Input Active Low reset signal for digital circuitry 6 VDDD Power VDD for Digital circuitry and PLL ...
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... EAR0N/SPEAKERN Output Negative Earpiece output (high power for Loud Speaker) 42 EAR0P/SPEAKERP Output Positive Earpiece output (high power for Loud Speaker) 41 GNDP0 Ground GND for RX Analog O/P circuitry (Audio Interface #0) 30 AUXTONE Input Auxiliary ringing/announcement input (to Loud Speaker outputs) Analog Audio Interface #3 Audio Interface #2 Audio Interface #1 Audio Interface #0 Auxiliary Tone Input MT92303 3 ...
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... MT92303 Functional Description The MT92303 Dual Codec provides complete audio to PCM interfaces including filtering and optional data companding as required by the ITU-T G.711 & G.712 recommendations. Programmable gain allows adjustment for a wide range sensitivities - two microphone amplifiers and four earpiece amplifiers are provided to allow connection to a handset, headset, auxiliary channel and microphone/speaker ...
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... Smoothing 1 order hi-pass @ 0-400Hz DAC 1.012Vrms @ 0dBm0 ‘DSP’ ‘Analog’ 0.611Vrms @ 0dBm0 ADC Anti-Alias 0dB to 22.5dB Filter in 1.5dB steps MT92303 1kHz 2kHz 3kHz -28dB to +2dB in 2dB steps Rec Filter Cross Point Bypass Control Cross 24dB Point Mic Pre-Amp ...
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... MT92303 Loud Speaker Drive The MT92303 provides four Audio Interfaces, all of which provide the same gain adjustments and output drive voltage levels. However, Audio Interface #0 has an output buffer which is capable of delivering more current than the others, and is intended for use with a loud speaker ...
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... The electret bias is programmed via one of the control registers, and provides a stable, low noise voltage which is derived from voltage-reference. The bias voltage is programmable from 0 to 2.52V (nominal steps, and has a nominal output noise level 300-3400Hz). MT92303 R1 Electret Microphone R2 the on-chip of 25uV (rms, 7 ...
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... Figures 8 and 9, it draws a bias current from the MICBIAS pin. The voltage across the ‘bottom’ bias resistor is monitored by the MICDETECT input and is used to set a ‘presence’ flag in the MT92303’s Status Register. This allows the external controller to determine whether or not the handset and headset are plugged-in ...
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... This clock samples the incoming data on DSTi at the 3/4 bit-cell position (the second rising clock edge) and makes data available on DSTo at the start of the bit-cell. A bit cell is the 2 clock cycles used to transfer 1 data bit. See Figure 17 in the electrical characteristics section for information. MT92303 Linear detailed timing 9 ...
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... Monitor byte (M). • Control/Indication byte (C/I). For the MT92303 only the B1 and B2 bytes are used, during the M and C/I bytes, Dout is tristate. The serial data streams are Din and Dout, the clock is DCL and the frame pulse is FSC, as shown in Figure 11. Data is arranged MSB first. ...
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... Channel Definition (SSI) In dual codec mode, codec0 data is transmitted first, either as 8-bit companded or 16-bit linear, then codec1 data and finally the status register. In single codec mode, the codec data is transmitted first and then the status register. 125us MT92303 CH6 CH7 C/I section for detailed ...
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... DATA2 becomes the data receive pin. The MT92303 processor mode (CPOL=0 and CPHA=0). This means that during a write to the MT92303 by the Motorola-type processor, output data from the DATA1 pin must be ignored (by the processor). This also means that input data on the DATA2 pin is ignored by the MT92303 during a valid read by the Motorola processor ...
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... This can be done by: • Running SCLK continuously. • Reading/Writing to another device (which could be a dummy) after each microport ‘write’. This will force SCLK active while CS is high. Future versions of the MT92303 may not require this ‘extra’ SCLK cycle ...
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... PLL is ‘enabled’ (if the PLL is Internal required). Clock System Reset Options The MT92303 has a ‘RESET’ mode in which all the Control Registers, the DSP, and all other latched functions are ‘reset’. This ‘RESET’ mode may be initiated in three different ways:- • ...
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... See note below. Note: When the ‘software’ reset is cleared as described above important that the SCLK clock edge is not regarded by the MT92303 as part of a Microport ‘read’ or ‘write’ operation. The ‘SCLK’ rising clock edge must consequently be applied while the CS pin is inactive (high) ...
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... MT92303 Address 00h/01h Write only 0 MUTE_V ‘DSP’ RX Mute 1 MUTE_S ‘DSP’ Sidetone Mute 2 PCM 0=Linear 1=Companded 3 u/A Law 0=A Law 1=u Law 4-7 - UNUSED (Don’t care) Address 02h/03h Write only 0 EN_CODEC Enable Codec 1 VOL[0] ’DSP’ RX Volume Control from -21dB to 0dB in 3dB steps. See table below ...
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... Codec: RX Hi-Pass-Filter (Registers x2) Codec: Sidetone Gain (Registers x2) -3dB Frequency (Hz) GAIN (dB) STG[3:0] -39 1000 -36 1001 -33 1010 -30 1011 -27 1100 -24 1101 -21 1110 -18 1111 MT92303 st order filter). See table below 0 40 100 150 200 300 400 Invalid GAIN (dB) -15 - ...
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... MT92303 Address 08h/09h Write only 0 DSPTEST[0] LOOPBACK (digital-to-digital). ‘0’ for normal operation, ‘1’ for loopback 1 DSPTEST[1] RESERVED (Defaults to ‘0’. Do not over-write with different value) 2 DSPTEST[2] RESERVED (Defaults to ‘0’. Do not over-write with different value) 3-7 - UNUSED (Don’t care) ...
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... GAIN (dB) RXG [3:0] -28 1000 -26 1001 -24 1010 -22 1011 -20 1100 -18 1101 -16 1110 -14 1111 RX ‘Analog’ Gain AUX GAIN (dB) RXG0 [3:0] -29 1000 -27 1001 -25 1010 -23 1011 -21.1 1100 -19.1 1101 -17.1 1110 -15.1 1111 #0 AUXTONE Gain MT92303 GAIN (dB) -12 - AUXGAIN (dB) -13.2 -11.2 -9.3 -7.4 -5.5 -3.6 -1 ...
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... MT92303 EB [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Address 10h Read/Write 0 EN_AUDIO_0 1 EN_AUDIO_1 Enable Audio Interfaces (RX ‘analog’ circuitry, Electret bias, Microphone detect, Auxtone) 2 EN_AUDIO_2 3 EN_AUDIO_3 4 EN_VREF Enable Voltage Reference (needed for all analog functions) 5 EN_TX0 Enable TX ‘analog’ circuitry. Also initiates the ‘TX offset correction’ routine. ...
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... Status-Channel Allocation ST-Bus mode 31) e.g. CHAN[4:0] = 01110 = Channel 14 2 CHAN[2] GCI mode e.g. CHAN[4:0] = XX110 = Channel 6 3 CHAN[3] SSI mode: ignored 4 CHAN[4] 5-7 - UNUSED (Don’t care) Cross-Point: Selection (Register x1) PCM Interface: Codec Channel Allocation (Register x2) PCM Interface: Status Channel Allocation (Register x1) MT92303 21 ...
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... MT92303 Address 15h Read/Write 0 PCM_BUS[0] Selects PCM Data Interface 00 = ST-Bus GCI SSI 1 PCM_BUS[1] 2 MUTEMODE3[0] Audio Interface #3: Mic Mute mode control (see section ‘Microphone Mute Detect’ and table below) 3 MUTEMODE3[1] 4 MUTEMODE2[0] Audio Interface #2: Mic Mute mode control (see section ‘Microphone Mute Detect’ and table below) ...
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... Audio Interface #2: ‘Mic Presence Detect’ signal 6-7 - UNUSED (Don’t care) General: Test (Register x1) ‡ for ‘gemulation mode’ testing ‡ for internal signal testing via DTSO pin. ‡ General: Test TX Analog (Register x1) ‡ for production testing Audio Interface: Status (Register x1) MT92303 ‡ ‡ 23 ...
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... MT92303 AC/DC Electrical Characteristics Absolute Maximum Ratings Characteristics Storage Temperature Supply Voltage Pin voltage relative to VDD Pin voltage relative to GND or SUB ‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics Ambient Temperature ...
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... Gain 0dB to 10.5dB 54 kOhms Gain 12dB to 22.5dB 80 kOhms Gain 24dB to 46.5dB 0 to +46 gain values available 0 +0.2 dB Gain 0dB to 22.5dB, 1kHz, 0dBm0 0 +0.3 dB Gain 24dB to 46.5dB, 1kHz, 0dBm0 1 rms Gain set to Minimum -90 dBm0 5 uV rms Gain set to Maximum -55 dBm0 MT92303 Comments Comments 25 ...
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... MT92303 Electret Bias, Mic Presence and Mic Mute Detect Characteristics measured at the MICBIAS pin relative to GND. All Detect parameters measured at the MICDETECT pin relative to GND. Characteristics Electret bias voltage ‘EBV’ Output noise Drive current capability Output resistance Supply rejection ‘Presence’ detect threshold (rising) ‘ ...
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... F0iS t 20 F0iH t 20 DSH t 20 DSS t DSD t ASHZ t C4H t C4L t DSH Bit 6 t DSD Bit 6 Figure 17 - ST-Bus Data Port Timing MT92303 Typ Max Units Test Notes 244.1 244 150 ns 150 =150pF =150pF ...
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... MT92303 PCM Serial Data Interface Timings (GCI) Characteristics DCL Period C4i/DCL/SCK Clock High C4i/DCL/SCK Clock Low F0i / FSC Setup F0i / FSC Hold ST-BUS/GCI Data Input Hold time ST-BUS/GCI Data Input Setup time GCI FSC to Data Delay (first bit) ST-BUS/GCI Data Output delay ...
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... AHZ SDS t 15 SDH t SCL t t SCP SCH Bit Bit 6 Figure 19 - SSI Data Port Timing MT92303 Typ Max Units Test Notes 1953 =150pF =150pF =150pF SCP t ...
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... MT92303 Microport Timings Characteristics Input Data Setup Input Data Hold Output Data Delay Serial Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Setup-Intel CS Setup-Motorola CS Hold CS to Output High Impedance DATA INPUT DATA1 t t IDS IDH SCLK t CSSI CS DATA2 (Input) ...
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... Set Mode - Write addr 15h Set System Clock Frequency and enable PLL (if required) - Write addr 16h Wait 1ms for PLL to settle (if used) Program Codec 0/1 - Write addr 00-07h Set TX Gains - Write addr 0A-0Bh Enable Codec 0/1 - Write addr 02-03h Set Cross-Point - Write addr 11h talk MT92303 31 ...
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... Decoupling capacitors should be as close to the pins as possible. • Decoupling for the Loud Speaker and Earpiece supplies may need to be increased. • Pins 4 and 5 are connected together in this example. In this configuration, the MT92303 uses an internal PLL to multiply the PCM serial clock (4.096MHz 20.48MHz (used internally). 32 100n ...
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... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...