MT92303 Zarlink Semiconductor, MT92303 Datasheet - Page 22

• Manufacturer Part Number: MT92303
• Manufacturer: Zarlink Semiconductor

MT92303
22
MUTEMODE[1:0]
5-7
0
1
2
3
4
5
6
7
0
1
2
3
4
FREQ [2:0]
Address 16h
Address 15h
Read/Write
Read/Write
000
001
010
011
100
101
110
111
00
01
10
11
MUTEMODE3[0]
MUTEMODE3[1]
MUTEMODE2[0]
MUTEMODE2[1]
PCM_BUS[0]
PCM_BUS[1]
SW_RESET
FREQ[0]
FREQ[1]
FREQ[2]
EN_PLL
MUTE[0]
MUTE[1]
-
Microphone path enabled (normal operation). ‘Mic Mute Detect’ signal ignored
Microphone path disabled (muted) while ‘Mic Mute Detect’ signal is high, and enabled
while low
Microphone path disabled (muted) while ‘Mic Mute Detect’ signal is high, but must be
re-enabled by the external controller
Microphone path disabled (muted). ‘Mic Mute Detect’ signal ignored
System Clock (MHz)
10.24 (spare)
System Clock frequency, ‘SYSCLK’. See table below
Note: Some frequencies need the internal PLL to be enabled
Enable PLL (only required for some SYSCLK frequencies). Allow 1ms to settle
‘Software Reset’ - see explanation in section ‘System Reset Options’
UNUSED (Don’t care)
Selects PCM Data Interface
00 = ST-Bus, 01 = GCI, 10 = SSI
Audio Interface #3: Mic Mute mode control
(see section ‘Microphone Mute Detect’ and table below)
Audio Interface #2: Mic Mute mode control
(see section ‘Microphone Mute Detect’ and table below)
Software mute for Audio Interface #0
Software mute for Audio Interface #1
20.48
2.048
4.096
10.24
20.0
25.0
50.0
General: System Clock Frequency, PLL and Software Reset (Register x1)
Mute Operation (see Figure 9)
General: Mode Control (Register x1)
Direct (PLL output not used)
Direct (PLL output not used)
Direct (PLL output not used)
Direct (PLL output not used)
Clocking Method
Internal PLL
Internal PLL
Internal PLL
Internal PLL
Preliminary Information
PLL Multiplier
x10
x10
x5
x2
x2
x5
x2
x2