MT92303 Zarlink Semiconductor, MT92303 Datasheet - Page 9

• Manufacturer Part Number: MT92303
• Manufacturer: Zarlink Semiconductor

Preliminary Information
close to the package as possible. The bandgap
voltage has a nominal value of 1.26V and may be
used by other external circuitry as long as this is not
allowed to interfere with the reference voltage. The
reference voltage is not designed to deliver current
so it should not be connected to a resistive load, or
an AC noise source which cannot be decoupled by
the external capacitor alone.
The reference voltage circuit may be powered up and
down under the control of one of the internal
registers. When it is powered up, the reference
voltage will take <1ms to settle.
PCM Interface (Voice & Status)
The TX and RX digitised voice data is accessed via
the PCM interface which can be programmed to work
in one of three modes. These are ST-bus, GCI and
SSI mode as described below. The contents of an
on-chip ‘Status’ register may also be read via this
interface.The DSTo/Dout/SDT pin is high impedance
when inactive - this allows multiple codecs to share
the PCM bus.
PCM codes which are equivalent to a ‘digital mW’
(0dBm0) for a 1kHz sinewave are shown in table 4.
ITU-T G.711 defines the peak coding level for A-law
as 3.14dBm0 and for u-Law as 3.17dBm0.
DSTo/D
DSTi/D
C4i/DCL/SCK
F0i/FSC/SC2
Pin Name
Table 3. PCM Interface Pin Description
out
in
/SRD
/STD Output Serial data
Type
Input Serial clock.
Input Frame Alignment.
Input Serial data
ST-Bus = 4.096MHz
GCI = 1.536 - 4.096MHz
SSI = 0.512 - 4.096MHz
ST-Bus active low pulse
GCI active high pulse
SSI active high
Description
The A-law and u-Law schemes use sign-magnitude
data, and the Linear system uses 2’s compliment.
The data words are shown as MSB first.
Table 4 also shows the coding for full-scale and ‘zero’
(‘quiet code’).
ST-Bus Interface
The ST-BUS consists of output (DSTo) and input
(DSTi) serial data streams, a synchronous clock
input signal (C4i), and a framing pulse input (F0i).
These are shown in Figure 10. The data streams
operate at 2048 kb/s and are Time Division
Multiplexed into 32 identical channels of 64 kb/s
bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to parse the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 uSecond period translating into an 8
kHz frame rate. Data is arranged MSB first. A valid
frame begins when F0i is logic low coincident with a
falling edge of C4i. Refer to Zarlink applications note
MSAN-126 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock samples the incoming data on DSTi at the
3/4 bit-cell position (the second rising clock edge)
and makes data available on DSTo at the start of the
bit-cell. A bit cell is the 2 clock cycles used to transfer
1 data bit. See Figure 17 in the electrical
characteristics
information.
Phase
+Full
Zero
-Full
-7/8
-5/8
-3/8
-1/8
1/8
3/8
5/8
7/8
00110100
00100001
00100001
00110100
10110100
10100001
10100001
10110100
00101010
11010101
10101010
A-Law
Table 4. PCM Coding
section
00011110
00001011
00001011
00011110
10011110
10001011
10001011
10011110
00000000
11111111
10000000
u-Law
for
1101110110000100
1010111010000100
1010111010000100
1101110110000100
0010001001111100
0101000101111100
0101000101111100
0010001001111100
1000000000000000
0000000000000000
0111111111111111
detailed
MT92303
Linear
timing
9