MT92303 Zarlink Semiconductor, MT92303 Datasheet - Page 15

• Manufacturer Part Number: MT92303
• Manufacturer: Zarlink Semiconductor

Preliminary Information
The ‘software’ reset is programmed via the Microport
Interface, and is cleared automatically by the next
rising edge on the Microport Interface’s serial clock
input (‘SCLK’). See note below.
Note: When the ‘software’ reset is cleared as
described above, it is important that the SCLK clock
edge is not regarded by the MT92303 as part of a
Microport ‘read’ or ‘write’ operation. The ‘SCLK’
rising clock edge must consequently be applied while
the CS pin is inactive (high). Future versions of the
MT92303 may use a different method to clear the
‘software’ reset.
Power-Down Mode
The individual circuits of the MT92303 are capable of
being powered-down when not needed. This allows
the operating current to be minimised, and it also
allows the whole chip to be powered-down into a
micro-power state if required.
The circuits are powered-down under the control of
the relevant register bits. In general, the circuitry is
powered-down after a power-on-reset or hardware or
software reset, and is usually ‘enabled’ when
required. To put the MT92303 into micro-power
mode, then all of the circuits listed below need to be
‘disabled’ by setting the register bits low. For
absolute minimum power consumption, the System
Clock must also be stopped.
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Loopback Testing
Digital-to-digital ‘loopback’ testing may be enabled by
the appropriate bit in the ‘DSP Test’ register. In this
mode, the voice data which is normally fed to the RX
DAC inputs is sent to the TX DSP inputs (which are
normally fed by the TX ADC).
The transfer of data from the RX domain to the TX
domain is not straightforward since the sample rates
and resolutions of the DAC and ADC are not the
same. This results in some scrambling of the data
and as a consequence, a sinewave input signal will
not result in a sinewave output signal. However, the
loopback path is formed from digital circuitry (PCM
port, DSP filtering, DSP gains) and will behave in a
strictly repeatable, bit-wise fashion. The integrity of
Audio Interfaces #0 to #3 (‘EN_AUDIO’ x4)
TX analog #0 and #1 (‘EN_TX’ x2)
Voltage reference (‘EN_VREF’ x1)
PLL (‘EN_PLL’ x1)
Codecs #0 and #1 (‘EN_CODEC’ x2)
the loopback path can consequently be verified by
the use of fixed digital vectors. To ensure a fixed,
repeatable response from the DSP circuitry, the
application of loopback vectors should be preceded
by a System Reset.
MT92303 Programming & Registers
All operating modes, power up/down, gain levels and
muting, electret biasing, filter cut-off’s etc are set by
the contents of the registers shown below. These are
all accessed via the microport. Some of the registers
are write-only, some are read-write, and the ‘Status’
register is read-only. The ‘hex’ addresses and read/
write access are shown at the top of each table. Note
that most of the registers are duplicated - there are
generally 2 addresses for registers which control the
Codecs, and 4 addresses for those which control the
Audio Interfaces.
Register Defaults
The MT92303 has an on-chip ‘Power On Reset’
circuit which is used to clear and initialize the
circuitry whenever power is applied to the device.
The RESETB pin may also be used to provide a
‘hardware’ reset which produces the same effect. In
this state, all the register bits are reset to ‘0’
Figure 22 shows a flow diagram with a suggested
register programming sequence.
MT92303
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