MT92303 Zarlink Semiconductor, MT92303 Datasheet - Page 10

• Manufacturer Part Number: MT92303
• Manufacturer: Zarlink Semiconductor

MT92303
Channel Definition (ST)
Each Codec requires 1 (companded PCM) or 2
(linear PCM) channels. In addition to these 2 or 4
channels there is a ‘status’ channel. The allocation of
these channels is fully programmable, subject to the
following:
•
•
This will allow multiple MT92303s to share the
ST-Bus (10 in companded and 6 in linear mode).
In the event of the codecs or the status register
erroneously having the same channel allocation, the
prioritisation is (highest first): codec0, codec1,
status. Only the highest priority has access to the
PCM channel.
General Circuit Interface (GCI)
In GCI mode the number of channels available in a
125us frame pulse period depends on the DCL clock
frequency, a DCL clock frequency of 1536kHz allows
3 channels, 2048kHz allows 4 channels and
4096kHz allows 8 channels.
10
DSTi/DSTo
DSTi/DSTo
Data-in and data-out are in the same channel
slot for the DSTi and DSTo streams.
In 16bit linear mode the 2 bytes are in adjacent
channels.
F0i
C4i
C4i
ch
0
Bit 7
ch
1
ch
2
ch
3
ch
4
Figure 10 - ST-Bus Channel Allocation in a Frame Pulse
Bit 6
ch
5
ch
6
ch
7
ch
8
Bit 5
ch
9
ch
10
ch
11
ch
12
32 ST-Bus Channels
C4i = 4096kHz
C4i = 4096kHz
Bit 4
ch
13
1 Channel
3.90625us
ch
14
125us
ch
15
Each channel is allocated 4 consecutive bytes which
are defined as:
•
•
•
For the MT92303 only the B1 and B2 bytes are used,
during the M and C/I bytes, Dout is tristate. The
serial data streams are Din and Dout, the clock is
DCL and the frame pulse is FSC, as shown in Figure
11. Data is arranged MSB first.
The channels selected must be compatible with the
DCL clock frequency being used. The ‘status’
register information is also output on one other
channel, in the B1 slot. GCI mode is enabled by
setting the appropriate bits in the control register.
The clock rate for GCI is double the bit rate. See
Figure 18 in the electrical characteristics section for
detailed timing information.
Channel Definition (GCI)
The PCM data will be output on the channels defined
by the Channel Allocation Registers. The Status
register is also output on one other channel on B1 as
defined by the Status Channel Allocation Register.
ch
16
PCM data bytes B1 and B2.
Monitor byte (M).
Control/Indication byte (C/I).
Bit 3
ch
17
ch
18
ch
19
ch
20
Bit 2
ch
21
ch
22
ch
23
Preliminary Information
ch
24
Bit 1
ch
25
ch
26
ch
27
ch
28
Bit 0
ch
29
ch
30
ch
31