MT92303 Zarlink Semiconductor, MT92303 Datasheet - Page 13

• Manufacturer Part Number: MT92303
• Manufacturer: Zarlink Semiconductor

Preliminary Information
transfer. As shown in Figures 14 and 15 the falling
edge of CS indicates to the MT92303 that a
microport transfer is about to begin. The first 8 clock
cycles of SCLK after the falling edge of CS are
always used to receive the Command/Address byte
from the microcontroller. The Command/Address
byte contains information detailing whether the
second byte transfer will be a read or a write
operation (read = 1, write = 0), and at what address.
The next 8 clock cycles are used to transfer the data
byte between the MT92303 and the microcontroller.
At the end of the two-byte transfer, CS is brought
high again to terminate the session. The rising edge
of CS will tri-state the DATA1 pin. The DATA1 pin will
remain tri-stated as long as CS is high. Intel
processors utilize Least Significant Bit (LSB) first
transmission while Motorola/National processors use
Most Significant Bit (MSB) first transmission. The
SCLK
DATA1
DATA1
Read
Write
CS
SCLK
DATA2
DATA1
DATA2
DATA1
output
output
Read
Write
input
input
CS
Rd
Wr
COMMAND/ADDRESS
Figure 15 - Microport Waveform (Motorola/National mode)
A
A
0
0
Rd
Wr
COMMAND/ADDRESS
A
A
A
A
1
1
5
5
Figure 14 - Microport Waveform (Intel mode)
A
A
A
A
2
2
4
4
A
A
A
A
3
3
3
3
A
A
A
A
4
4
2
2
A
A
A
A
5
5
1
1
X
X
A
A
0
0
X
X
MT92303 microport automatically accommodates
these two schemes for normal data bytes. However,
to ensure timely decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel and Motorola/National operations.
Note: SCLK needs to be pulsed once after CS is
deactivated at the end of a microport ‘write’. This can
be done by:
•
•
Future versions of the MT92303 may not require this
‘extra’ SCLK cycle.
D
Running SCLK continuously.
Reading/Writing to another device (which could
be a dummy) after each microport ‘write’. This
will force SCLK active while CS is high.
D
0
0
D
D
D
D
1
1
X
X
7
7
D
D
D
D
2
2
X
X
6
6
D
D
DATA
D
D
3
3
X
X
5
5
D
D
D
D
4
4
X
X
DATA
4
4
D
D
D
D
5
5
X
X
3
3
D
D
D
D
6
6
X
X
2
2
D
D
D
D
7
7
X
X
1
1
MT92303
D
D
X
X
0
0
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