MT92303 Zarlink Semiconductor, MT92303 Datasheet - Page 31

• Manufacturer Part Number: MT92303
• Manufacturer: Zarlink Semiconductor

Preliminary Information
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Run F0i clock for 128 periods (16ms) for TX Offset Cancellation
SYSCLK must be present before PLL is enabled.
Frequency register must be written-to before either Codec is enabled.
TX 0/1 must be enabled after VREF has settled.
Figure 22 - Suggested Microport Programming Sequence
Set RX Gains & Electret Bias - Write addr 0C-0Fh
* Enable TX 0/1 and Audio 0-3 - Write addr 10h
Set PCM & Status Channel - Write addr 12-14h
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or Hardware RESET - ‘RESETB’
or Software RESET - Write addr 16h
Program Codec 0/1 - Write addr 00-07h
Set Cross-Point - Write addr 11h
Enable VREF - Write addr 10h
Enable Codec 0/1 - Write addr 02-03h
Wait 1ms for PLL to settle (if used)
Set TX Gains - Write addr 0A-0Bh
Power-On Reset
Wait 1ms for VREF to settle
Set Mode - Write addr 15h
Set System Clock Frequency
and enable PLL (if required)
- Write addr 16h
talk
MT92303
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