MT9300 Mitel Networks Corporation, MT9300 Datasheet - Page 6

• Manufacturer Part Number: MT9300
• Description: Multi-channel Voice Echo CANceller
• Manufacturer: Mitel Networks Corporation

MT9300
Non-Linear Processor (NLP)
After echo cancellation, there is always a small
amount of residual echo which may still be audible.
The MT9300 uses an NLP to remove residual echo
signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This
threshold depends upon the level of the Rin (Lrin)
reference signal as well as the programmed value of
the
(NLPTHR). TSUP can be calculated by the following
equation:
where
Threshold register value and Lrin is the relative
power level expressed in dBm0.
When the level of residual error signal falls below
TSUP, the NLP is activated further attenuating the
residual signal to less than -65dBm0. To prevent a
perceived decrease in background noise due to the
activation of the NLP, a spectrally-shaped comfort
noise, equivalent in power level to the background
noise, is injected. This keeps the perceived noise
level constant. Consequently, the user does not hear
the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the
NLPDis bit to “1” in Control Register 2.
The NLPTHR register is 16 bits wide. The register
value in hexadecimal can be calculated with the
following equation:
where 0 < NLPTHR
The comfort noise injection can be disabled by
setting the INJDis bit to “1” in Control Register A1/
B1.
It should be noted that the NLPTHR is valid and the
comfort noise injection is active only when the NLP is
enabled.
Disable Tone Detector
G.165 recommendation defines the disable tone as
having
( 21Hz) sine wave, a power level between -6 to
-31dBm0, and a phase reversal of 180 degrees ( 25
degrees) every 450ms ( 25ms). If the disable tone is
6
Non-Linear
NLPTHR
NLPTHR
the
TSUP = Lrin + 20log
following
(hex)
(dec)
Processor
is
= hex(NLPTHR
the
< 1
characteristics:
Non-Linear
10
(NLPTHR)
Threshold
(dec)
* 32768)
Processor
2100
register
Hz
present for a minimum of one second with at least
one phase reversal, the Tone Detector will trigger.
G.164 recommendation defines the disable tone as a
2100 Hz ( 21Hz) sine wave with a power level
between 0 to -31dBm0. If the disable tone is present
for a minimum of 400 milliseconds, with or without
phase reversal, the Tone Detector will trigger.
The MT9300 has two Tone Detectors per channels
(for a total of 64) in order to monitor the occurrence
of a valid disable tone on both Rin and Sin. Upon
detection of a disable tone, TD bit of the Status
Register will indicate logic high and an interrupt is
generated (i.e. IRQ pin low). Refer to Figure 4 and to
the Interrupts section.
Once a Tone Detector has been triggered, there is
no longer a need for a valid disable tone (G.164 or
G.165) to maintain Tone Detector status (i.e. TD bit
high). The Tone Detector status will only release (i.e.
TD bit low) if the signals Rin and Sin fall below -
30dBm0, in the frequency range of 390Hz to 700Hz,
and below -34dBm0, in the frequency range of
700Hz to 3400Hz, for at least 400ms. Whenever a
Tone Detector releases, an interrupt is generated
(i.e. IRQ pin low).
The selection between G.165 and G.164 tone
disable is controlled by the PHDis bit in Control
Register 2 on a per channel basis. When the PHDis
bit is set to 1, G.164 tone disable requirements are
selected.
In response to a valid disable tone, the echo
canceller must be switched from the Enable
Adaptation state to the Bypass state. This can be
done in two ways, automatically or externally. In
automatic mode, the Tone Detectors internally
control the switching between Enable Adaptation and
Bypass states. The automatic mode can be activated
by setting the AutoTD bit in Control Register 2 to
high. In external mode, an external controller is
needed to service the interrupts and poll the TD bits
Rin
Sin
Rin
Sin
Figure 4 - Disable Tone Detection
Tone
Tone
Tone
Tone
Echo Canceller A
Echo Canceller B
Detector
Detector
Detector
Detector
Advance Information
Status reg
Status reg
TD
TD bit
ECA
ECB
bit