MT9075A Mitel Networks Corporation, MT9075A Datasheet - Page 3

• Manufacturer Part Number: MT9075A
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Preliminary Information
Pin Description
PLCC MQFP
13 -
10
11
12
16
1
2
3
4
5
6
7
8
9
Pin #
86-
66
67
68
69
70
71
72
73
74
83
84
85
89
D0 - D3 Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the
RESET
DS/RD
Name
OSC1
OSC2
CSTo
DSTo
CSTi
DSTi
V
V
IRQ
CS
SS
DD
Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2 where a
crystal is used, or is directly driven when a 20.000 MHz oscillator is employed (see
Figures 6 and 7). Not suitable for TTL compatible oscillator.
Oscillator Output. Not suitable for driving other devices.
Negative Power Supply (Input). Digital ground.
Positive Power Supply (Input). Digital supply (+5V
Control ST-BUS Output. CSTo carries one of the following two serial streams for CAS
and CCS respectively:
(i) A 2.048 Mbit/s ST-BUS status stream which contains the 30 receive signalling nibbles
(ABCDZZZZ or ZZZZABCD). The most significant nibbles of each ST-BUS time slot are
valid and the least significant nibbles of each ST-BUS time slot are tristated when control
bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the valid
and tristated nibbles is reversed.
(ii) A 64 kb/s output when the 64 KHz common channel signalling option is selected
(page 01H, address 1AH, bit 0, 64KCCS =1) for channel 16.
Control ST-BUS Input. CSTi carries one of the following two serial streams for CAS and
CCS respectively:
(i) A 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit signalling
nibbles (ABCDXXXX or XXXXABCD) when page 01H, address 1AH, bit 3, RPSIG=0.
When RPSIG=1 this pin has no function. The most significant nibbles of each ST-BUS
time slot are valid and the least significant nibbles of each ST-BUS time slot are ignored
when control bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position
of the valid and ignored nibbles is reversed.
(ii) A 64 kb/s input when the 64 KHz common channel signalling option is selected (page
01H, address 1AH, bit 0, 64KCCS =1) for channel 16.
Data ST-BUS Output. A 2.048 Mbit/s serial stream which contains the 30 PCM or
data channels received on the PCM 30 line.
Data ST-BUS Input. A 2.048 Mbit/s serial stream which contains the 30 PCM or data
channels to be transmitted on the PCM 30 line.
Data/Read Strobe (Input).
In Motorola mode (DS), this input is the active low data strobe of the microprocessor
interface.
In Intel mode (RD), this input is the active low read strobe of the microprocessor
interface.
Chip Select (Input). This active low input enables the non-multiplexed parallel
microprocessor interface of the MT9075A. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
RESET (Input). This active low input puts the MT9075A in a reset condition. RESET
should be set to high for normal operation. The MT9075A should be reset after power-
up. The RESET pin must be held low for a minimum of 1 sec. to reset the device
properly.
Interrupt Request (Output). A low on this output pin indicates that an interrupt request
is presented. IRQ is an open drain output that should be connected to V
pull-up resistor. An active low CS signal is not required for this pin to function.
bidirectional data bus of the microprocessor interface (D0 is the least significant bit).
Description
5%).
MT9075A
DD
through a
4-131