MT9075A Mitel Networks Corporation, MT9075A Datasheet - Page 59

• Manufacturer Part Number: MT9075A
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Preliminary Information
3, 2
1, 0
Bit
Rxstat2,
Txstat2,
Rxstat1
Txstat1
Name
(Pages 0BH & 0CH, Address 14H)
Table 84 - HDLC Status Register
Transmit
indicate the status of the TX FIFO
as follows:
Receive
indicate the status of the RX FIFO
as follows:
Rxsta
Txsta
t2
t2
0
0
1
1
0
0
1
1
Functional Description
Rxsta
t1
Txsta
t1
0
1
0
1
0
1
0
1
Status.
Status.
TX FIFO full up to
the selected status
level or more. See
Table 93.
The number of bytes
in the TX FIFO has
reached
exceeded
selected
threshold level. See
Table 94.
TX FIFO empty.
The number of bytes
in the TX FIFO is
less
selected
threshold level. See
Table 94.
RX FIFO empty.
The number of bytes
in the RX FIFO is
less
selected
level. See Table 94.
RX FIFO full up to
the selected status
level or more. See
Table 93.
The number of bytes
in the RX FIFO has
reached
exceeded
selected
threshold level. See
Table 94.
RX FIFO Status
TX FIFO Status
These
These
than
than
threshold
interrupt
interrupt
interrupt
bits
bits
the
the
the
the
or
or
Bit
7
6
5
4
3
2
1
0
Seven
Name
Rxfrst
Cycle
Txfrst
Intsel
Tcrci
Table 85 - HDLC Control Register 2
RSV
RSV
(Pages 0BH & 0CH, Address 15H)
Interrupt Selection. When one, this
bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO
underrun (TXunder). When zero,
this interrupt will reflect a frame
abort (FA).
When one, this bit will cause the
transmit byte count to cycle through
the value loaded into the Transmit
Byte Count Register.
Transmit CRC Inhibited. When
one, this bit will inhibit transmission
of the CRC. That is, the transmitter
will not insert the computed CRC
onto the bit stream after seeing the
EOP tag byte. This is used in V.120
terminal adaptation for synchronous
protocol sensitive UI frames.
Seven Bits Address Recognition.
When one, this bit will enable seven
bits of address recognition in the
first address byte. The received
address byte must have bit 0 equal
to 1 which indicates a single
address byte is being received.
Reserved, must be zero for normal
operation.
Reserved, must be zero for normal
operation.
RX FIFO Reset. When one, the RX
FIFO will be reset. This causes the
receiver to be disabled until the next
reception of a flag. The status
register will identify the FIFO as
being empty. However, the actual
bit values in the RX FIFO will not be
reset.
TX FIFO Reset. When one, the TX
FIFO will be reset. The Status
Register will identify the FIFO as
being empty. This bit will be reset
when data is written to the TX FIFO.
However, the actual bit values of
data in the TX FIFO will not be
reset. It is cleared by the next write
to the TX FIFO.
Functional Description
MT9075A
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