MT9075A Mitel Networks Corporation, MT9075A Datasheet - Page 61

• Manufacturer Part Number: MT9075A
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Preliminary Information
7 - 0 Crc7 - 0 The LSB byte of the CRC received
7 - 0 Cnt7 - 0 The
(Pages 0BH & 0CH, Address 1BH) (continued)
Bit
Bit
Bit
7
Table 91 - HDLC Test Control Register
Table 90 - Transmit Byte Count register
Table 89 - Receive CRC LSB Register
Name
Name
Name
HRST
(Pages 0BH & 0CH, Address 19H)
(Pages B & C, Address 1AH)
from the transmitter. These bits are
as the transmitter sent them; that is,
most
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
Register. It is used to indicate the
length of the packet about to be
transmitted.
reaches the count of one, the next
write to the Tx FIFO will be tagged
as an end of packet byte. The
counter decrements at the end of
the write to the Tx FIFO. If the Cycle
bit of Control Register 2 is set high,
the counter will cycle through the
programmed value continuously.
HDLC Reset. When this bit is set to
one, the HDLC will be reset. This is
similar to RESET being applied, the
only difference being that this bit will
not be reset automatically. This bit
can only be reset by writing a zero
twice to this location or applying
RESET.
Functional Description
Functional Description
Functional Description
significant
Transmit
When
bit
Byte
this
first
register
Count
and
Bit
6
5
4
3
2
1
0
Table 91 - HDLC Test Control Register
RTloop
Name
Hloop
RSV
RSV
RSV
RSV
Ftst
(Pages 0BH & 0CH, Address 1BH)
RT Loopback. When this bit is set
to one, receive to transmit HDLC
loopback will be activated. Receive
data,
indication, but not including flags or
CRC, will be written to the TX FIFO
as well as the RX FIFO. When the
transmitter is enabled, this data will
be transmitted as though written by
the microprocessor. Both good and
bad packets will be looped back.
Receive to transmit loopback may
also be accomplished by reading
the
microprocessor and writing these
bytes, with appropriate tags, into the
TX FIFO.
Reserved; must be set to 0 for
normal operation.
Reserved; must be set to 0 for
normal operation.
Reserved; must be set to 0 for
normal operation.
FIFO Test. This bit when set to one
allows the writing to the RX FIFO
and reading of the TX FIFO through
the microprocessor to allow more
efficient testing of the FIFO status/
interrupt functionality. This is done
by making a TX FIFO write become
a RX FIFO write and a RX FIFO
read become a TX FIFO read. In
addition, EOP/FA and RQ8/RQ9 are
re-defined to be accessible (i.e. RX
write causes EOP/FA to go to RX
fifo input; TX read looks at output of
TX FIFO through RQ8/RQ9 bits).
Reserved; must be set to 0 for
normal operation.
TR Loopback. When high, transmit
to receive HDLC loopback will be
activated. The packetized transmit
data will be looped back to the
receive input. RxEN and TxEN bits
must also be enabled.
Functional Description
RX
including
FIFO
end
MT9075A
using
of
packet
4-189
the