MT8976 Mitel Networks Corporation, MT8976 Datasheet
MT8976
Available stocks
Related parts for MT8976
MT8976 Summary of contents
Page 1
... MT8976AP Description The MT8976 is Mitel’s second generation T1 interface solution. The MT8976 meets the Extended Super Frame format (ESF), the current D3/D4 format and is compatible with SLC-96 systems. The MT8976 interfaces to DS1 1.544 Mbit/sec digital trunk. 2 Frame Elastic Buffer with Slip Control ...
Page 2
... MT8976 ISO-CMOS 1 TxA 28 VDD 2 TxB DSTo 26 F0i E1.5i 5 RxA 24 C1. RxB RxSF 7 RxD 22 TxSF 8 CSTi1 21 C2i 9 TxFDL 20 RxFDL 10 TxFDLClk 19 DSTi RxFDLClk 12 17 CSTi0 CSTo 13 16 E8Ko XSt 14 VSS 15 XCtl 28 PIN CERDIP/PDIP Pin Description Pin # Name DIP PLCC 1 2 TxA Transmit A Output ...
Page 3
... RxD, RxA and RxB F0i Frame Pulse Input. This is the frame synchronization signal which defines the beginning of the 32 channel ST-BUS frame Internal Connection. Tied Positive Power Supply Input. +5V ± 5%. DD ISO-CMOS Description bit pattern in SLC-96 S for normal operation. SS MT8976 4-31 ...
Page 4
... MT8976 ISO-CMOS Functional Timing Diagrams C2i DSTi DSTo CSTi0/CSTi1 CSTo E1. INT DATA DS1 AMI LINE SIGNAL RxA RxB RxD E8Ko C1.5i INT DATA TxA TxB DS1 AMI LINE SIGNAL 4-32 125 Sec • • • • ...
Page 5
... MT8976 ISO-CMOS 4-33 ...
Page 6
... ST-BUS stream, and one of these 64 kbit/s channels is known as an ST-BUS channel. The system side of the MT8976 is made up of ST- BUS inputs and outputs, i.e., control inputs and outputs (CSTi/o) and data inputs and outputs (DSTi/o). These signals are functionally represented in Figure 3 ...
Page 7
... The RxSF output functions or T normally and indicates the superframe boundaries based on the synchronization pattern in the F received bit position. Zero Code Suppression In this The combination of bits 5 and 6 in Master Control Word 1 allow one of three zero code suppression MT8976 th S 4-35 ...
Page 8
... The MT8976 also has a per channel loopback mode. See Table 6 and the following section for more information. Per Channel Control Features ...
Page 9
... It will be reset when the device resynchronizes. The mimic bit, the terminal framing error bit and the CRC error counter can be used separately or together to decide if the receiver should be forced to reframe. MT8976 ISO-CMOS error T 4-37 ...
Page 10
... MT8976 ISO-CMOS Frame † Resynchronization Concentrator ...
Page 11
... For example, if the channel count in the phase status word is seen to increase over time, the feedback applied to the VCO is used to decrease the system clock frequency until a reversal in the trend is observed. Description Description MT8976 ISO-CMOS 4-39 ...
Page 12
... Word Table 11. Per Channel Status Word Output on CSTo The elastic buffer in the MT8976 permits the device to handle eight channels of jitter/wander (see description of elastic buffer in the next section). In order to prevent slips from occurring, the frequency corrections would have to be implemented such that the deviation in the phase status word is limited to eight channels peak to peak ...
Page 13
... Clock and Framing Signals The MT8976 requires one 2.048 MHz clock (C2i) and an 8 kHz framing signal for the ST-BUS side. Figure 12 illustrates the relationship between the two signals. The framing signal is used to delimit individual 32 channel ST-BUS frames ...
Page 14
... MT8976 ISO-CMOS Hunt Mode Candidate Candidate Verify Candidate In sync New Frame Position * Note: Only when in ESF mode and CRC option is enabled. Figure 8 - Off-Line Framer State Diagram pointer and the ST-BUS read pointer will begin to decrease over time. When this delay approaches the ...
Page 15
... An external line driver circuit is required in order to interface the device to twisted pair cabling. The split phase unipolar signals output by the MT8976 at TxA and TxB are used by the line driver circuit to generate a bipolar AMI signal. The line driver is transformer coupled to an equalization circuit and the DS1 line ...
Page 16
... AAA AAA AAA AAA AAA AAA AA AA AAA AAA AAA AAA AAA AAA AAA AAA AAA Reframe Time (msec) Figure 9 - Reframe Time MT8976 TxA DSTi TxB DSTo CSTi0 CSTo CSTi1 • RxA F0i RxB C2i C1.5i RxD TxFDL TxFDLClk TxSF ...
Page 17
... IRQ F0i lACK MMS +5V Figure 11 - Using the MT8976 in a Parallel Bus Environment the STPA transmit RAM’s Tx0, Tx1, information is read at receive RAM Rx0. In addition, into a unipolar interrupts can be set up to notify the system in case of slips, loss of sync, alarms, violations, etc. ...
Page 18
... MT8976 ISO-CMOS Absolute Maximum Ratings* Parameter 1 Power Supplies with respect Voltage on any pin other than supplies 3 Current at any pin other than supplies 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ...
Page 19
... TxSFS Frame 1 Bit Bit Bit Bit P20 t W20 t t FPS FPH t FPW t FPOD t FPOD Frame 1 t TxSFH MT8976 ISO-CMOS Units Test Conditions 488 ns P20 50pF Load s s Frame 2 Bit Bit Bit Bit W20 t ...
Page 20
... MT8976 ISO-CMOS AC Electrical Characteristics Characteristics 1 E1.5i Clock Period 2 E1.5i Clock Width High or Low † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are and are for design aid only; not guaranteed and not subject to production testing. DS1 BIT CELLS FOR RECEPTION 2 ...
Page 21
... C2i 0.8V 2.0V XSt 0.8V t XCD Channel 17 • • • Bit 2 t 8OD t t 8OL 8F Figure 18 - E8Ko Timing MT8976 ISO-CMOS Units Test Conditions Load Load Load Load Load Load . ST-BUS Bit Cell Boundary Between Bit 2 Channel 30 and Bit 1 Channel 30 ...
Page 22
... MT8976 ISO-CMOS AC Electrical Characteristics Parameters 1 Transmit Steering Delay 2 Transmit Steering Transition Time 3 Received Steering Setup Time 4 Received Steering Hold Time 5 Received Data Setup Time 6 Received Data Hold Time 7 C1.5i Period 8 C1.5i Pulse Width High or Low † Timing is over recommended temperature & power supply voltage ranges. ...
Page 23
... Sym Min Typ Max t 110 DLS t 70 DLH t DLOD t FRCD t TFCD Frame 1 t DLOD Figure 22 - Facility Data Link Timing MT8976 ISO-CMOS Units Test Conditions Load 185 50 pF Load 135 Load . Frame 2 t TFCD t t DLS DLH ...
Page 24
... MT8976 ISO-CMOS CHANNEL CHANNEL • • • • • • • • NB: Numbering BIT 7 differs from Fig 24. Figure 23 - Format of 2048 kbit/s ST-BUS Streams CHANNEL CHANNEL S Bit 24 1 (1/1.544) s NB: Numbering differs from Fig 23. 4-52 125 s CHANNEL 30 (8/2.048) s BIT 4 BIT 5 BIT 3 BIT 6 ...
Page 25
... High to Low Transition A Txt. Sig. Bit ESFYLW MFSYNC 1 Detected 1 Not Detected 0 Not 0 Detected Detected BIPOLAR VIOLATION COUNT Phase Status Word (Channel 3, CSTo) A Rec’d. Sig. Bit MT8976 ISO-CMOS 2 1 ESFYLW Robbed Bit YLALR 1 Enabled 1 Disabled 1 Enabled 0 Disabled 0 Enabled 0 Disabled SLC-96 CRC/MIMIC Maint ...
Page 26
... MT8976 ISO-CMOS NOTES: 4-54 ...